Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gate stacks separate from FE capacitors of these cells. An example memory cell may be implemented as an IC device that includes a support structure (e.g., a substrate) and a transistor provided over the support structure and including a gate stack. The IC device also includes a FE capacitor having a first capacitor electrode, a second capacitor electrode, and a capacitor insulator of a FE material between the first capacitor electrode and the second capacitor electrode, where the FE capacitor is separate from the gate stack (i.e., is not integrated within the gate stack and does not have any layers that are part of the gate stack). The IC device further includes an interconnect structure, configured to electrically couple the gate stack and the first capacitor electrode.

Abstract: A box package containing stacked disposable absorbent articles is disclosed. The package has a pair of top flaps, and a handle cutout on each flap. In one embodiment a handle reinforcing material may be disposed between the handle cutouts. In one embodiment the handle cutouts may be partial, and attached portions of material forming residual cutout flaps may remain attached within the cutouts. Other structural elements may be present to maximize economy of space while maintaining structural integrity, conserving materials and providing a package that is convenient for consumers.