Patents by Inventor Jack Kang
Jack Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240137062Abstract: Disclosed herein is a case or cover for protecting the housing of a folding portable electronic device such as a smart phone with a folding display. The case or cover includes a first and second portion hingedly joined to a hinge protecting portion. The case or cover allows the encase phone to lie flat when in the fully opened position and included thinner first and second case portions proximate to the hinge cover to minimize the gaps between the case portions during the transition from a fully open to a fully closed position.Type: ApplicationFiled: October 17, 2023Publication date: April 25, 2024Inventors: Jack Dufelmeier, Richard Kang
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Publication number: 20240085946Abstract: Disclosed herein is an improved packaging for a portable electronic device such as a smartphone. The packaging included features that allow the packaging to be used as an alignment or guide device to apply a screen protector to a screen of the portable electronic device.Type: ApplicationFiled: September 11, 2023Publication date: March 14, 2024Inventors: Jack Dufelmeier, Richard Kang
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Patent number: 8850169Abstract: A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.Type: GrantFiled: July 1, 2013Date of Patent: September 30, 2014Assignee: Marvell International Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Patent number: 8799929Abstract: A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.Type: GrantFiled: April 15, 2013Date of Patent: August 5, 2014Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Yu-Chi Chuang
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Publication number: 20130247072Abstract: A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.Type: ApplicationFiled: April 15, 2013Publication date: September 19, 2013Applicant: Marvell World Trade Ltd.Inventors: Jack Kang, Yu-Chi Chuang
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Patent number: 8539212Abstract: Systems, apparatuses, and methods for determinative branch prediction indexing are described herein. The determinative branch prediction indexing method includes receiving a program counter address for a branch instruction, dynamically selecting a branch indexing scheme from a plurality of branch indexing schemes, and generating a branch prediction index based at least in part on selected branch indexing scheme and the program counter address. Other embodiments may be described and claimed.Type: GrantFiled: August 31, 2012Date of Patent: September 17, 2013Assignee: Marvell International Ltd.Inventors: Jack Kang, Yu-Chi Chuang
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Patent number: 8478971Abstract: A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.Type: GrantFiled: December 19, 2011Date of Patent: July 2, 2013Assignee: Marvell International Ltd.Inventors: Jack Kang, Yu-Chi Chuang, Hsi-Cheng Chu
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Patent number: 8478972Abstract: A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread and when the instruction execution thread is in an active mode. The method further includes switching a second instruction execution thread to the active mode when the cycle count corresponding to the first instruction execution thread is complete, and fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread.Type: GrantFiled: September 28, 2011Date of Patent: July 2, 2013Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Hsi-Cheng Chu
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Patent number: 8473728Abstract: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.Type: GrantFiled: May 24, 2012Date of Patent: June 25, 2013Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Patent number: 8468326Abstract: A hardware module configured to perform single instructions faster than is possible in software running on the microprocessor. In one implementation, the hardware module is configured to perform a single count instruction, including - counting a number of “ones” contained in a first register; and storing, in a second register, the count of the number of “ones” contained in the first register.Type: GrantFiled: August 3, 2009Date of Patent: June 18, 2013Assignee: Marvell International Ltd.Inventors: Jack Kang, Jianwei Bei, Shanker Rao Donthineni, Manish Kumar, Victor Lin, Justin Lau
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Patent number: 8424021Abstract: A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.Type: GrantFiled: October 21, 2011Date of Patent: April 16, 2013Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Yu-Chi Chuang
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Publication number: 20120239915Abstract: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.Type: ApplicationFiled: May 24, 2012Publication date: September 20, 2012Inventors: Jack Kang, His-Cheng Chu, Yu-Chi Chuang
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Patent number: 8261049Abstract: Systems, apparatuses, and methods for determinative branch prediction indexing are described herein. The determinative branch prediction indexing method includes receiving a program counter address for a branch instruction, dynamically selecting a branch indexing scheme from a plurality of branch indexing schemes, and generating a branch prediction index based at least in part on selected branch indexing scheme and the program counter address. Other embodiments may be described and claimed.Type: GrantFiled: April 9, 2008Date of Patent: September 4, 2012Assignee: Marvell International Ltd.Inventors: Jack Kang, Yu-Chi Chuang
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Patent number: 8190866Abstract: Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another.Type: GrantFiled: January 10, 2011Date of Patent: May 29, 2012Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Publication number: 20120066479Abstract: A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread and when the instruction execution thread is in an active mode. The method further includes switching a second instruction execution thread to the active mode when the cycle count corresponding to the first instruction execution thread is complete, and fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread.Type: ApplicationFiled: September 28, 2011Publication date: March 15, 2012Inventors: Jack Kang, Hsi-Cheng Chu
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Publication number: 20120036518Abstract: A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.Type: ApplicationFiled: October 21, 2011Publication date: February 9, 2012Inventors: Jack Kang, Yu-Chi Chuang
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Patent number: 8082427Abstract: A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coupled to an instruction dispatch block, including thread-control registers for selectively disabling threads. In various embodiments, the multithread processing device may include a thread-operation register for selectively providing a lock to a first thread to prevent a second thread from disabling the first thread while the first thread has the lock. In still further embodiments, the multithread processing device may be configured to atomically disable and release a lock held by a thread. Other embodiments may be described and claimed.Type: GrantFiled: July 7, 2010Date of Patent: December 20, 2011Assignee: Marvell International Ltd.Inventors: Jack Kang, Hsi-Cheng Chu, Yu-Chi Chuang
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Patent number: 8046775Abstract: A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth allocation mode associated with the detected event, and allocating a plurality of execution cycles of an instruction execution period of a processor core among a plurality of instruction execution threads based at least in part on the selected bandwidth allocation mode. Other embodiments may be described and claimed.Type: GrantFiled: July 9, 2007Date of Patent: October 25, 2011Assignee: Marvell World Trade Ltd.Inventors: Jack Kang, Yu-Chi Chuang
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Patent number: D879730Type: GrantFiled: December 18, 2018Date of Patent: March 31, 2020Assignee: SiFive, Inc.Inventors: Jack Kang, David Lee, Jeffrey Mulhausen
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Patent number: D900044Type: GrantFiled: March 30, 2020Date of Patent: October 27, 2020Assignee: SiFive, Inc.Inventors: Jack Kang, David Lee, Jeffrey Mulhausen