Patents by Inventor Jack L. Glenn
Jack L. Glenn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11506621Abstract: A method for assessing a thermal path associated with an integrated circuit includes identifying a heat application mode based on a design type of the integrated circuit. The method also includes measuring a first temperature of at least one thermal sensing device associated with the integrated circuit. The method also includes applying heat to at least a portion of the integrated circuit according to the heat application mode. The method also includes measuring a second temperature of the at least one thermal sensing device. The method also includes determining a difference between the first temperature and the second temperature. The method also includes determining whether a thermal path between the integrated circuit and an associated substrate is sufficient based on a comparison of the difference between the first temperature and the second temperature with a predetermined difference between an initial temperature and a subsequent temperature of the at least one thermal sensing device.Type: GrantFiled: March 1, 2019Date of Patent: November 22, 2022Assignee: DELPHI TECHNOLOGIES IP LIMITEDInventors: Gregg N. Francisco, Kevin M. Gertiser, Jack L. Glenn, Narendra J. Mane, Thomas E. Pritchett, Soumyajit Routh, Kok Wee Yeo
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Patent number: 11323126Abstract: An electronic circuit includes a first pin corresponding to a reference signal and a second pin corresponding to an external resistor, the external resistor being connected on a first side to the second pin and connected on a second side to ground. The apparatus also includes a first oscillator having a first frequency loop configured to: receive, via the first pin, the reference signal; receive, via the second pin, a current associated with voltage applied to the external resistor; and lock a first frequency output at a frequency associated with the reference signal. The apparatus also includes a second oscillator having a second frequency loop configured to: receive the first frequency output; scale the frequency of the first frequency output; and lock a second frequency output at the scaled frequency of the first frequency output.Type: GrantFiled: April 28, 2021Date of Patent: May 3, 2022Assignee: Delphi Technologies IP LimitedInventors: Steven H. Rogers, Jack L. Glenn
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Patent number: 11293808Abstract: A method includes, responsive to an application of power to an IC, self-initializing the IC by asserting a reset signal for a reset period. Self-initializing the IC also includes, in response to an expiration of the reset period, deasserting the reset signal. Self-initializing the IC also includes, responsive to deasserting the reset signal, automatically obtaining first temperature data from at least one thermal sensing device associated with a die of the IC, and storing the first temperature data in a storage component of the IC.Type: GrantFiled: June 30, 2021Date of Patent: April 5, 2022Assignee: Delphi Technologies IP LimitedInventors: Soumyajit Routh, Kevin M. Gertiser, Jack L. Glenn, John Mark Dikeman, Daniel C. Penrod
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Publication number: 20200313937Abstract: A CAN transceiver includes a first terminal which receives a transmit signal from a CAN microcontroller. A splitter unit transmits a signal derived from the transmit signal to a CAN bus a via bus connection. A unit receives signals from the CAN bus via the bus connection. A second terminal sends a receive signal derived from the received signals to the CAN microcontroller. The transmit and receive signals include a pulsed signal waveform which represents data bits. Delay circuits apply a deliberate delay to the rising or falling edge of pulses of the transmit signal and/or a deliberate delay to the rising or falling edge of pulses of the receive signal.Type: ApplicationFiled: March 25, 2019Publication date: October 1, 2020Inventor: Jack L. Glenn
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Patent number: 10778481Abstract: A CAN transceiver includes a first terminal which receives a transmit signal from a CAN microcontroller. A splitter unit transmits a signal derived from the transmit signal to a CAN bus a via bus connection. A unit receives signals from the CAN bus via the bus connection. A second terminal sends a receive signal derived from the received signals to the CAN microcontroller. The transmit and receive signals include a pulsed signal waveform which represents data bits. Delay circuits apply a deliberate delay to the rising or falling edge of pulses of the transmit signal and/or a deliberate delay to the rising or falling edge of pulses of the receive signal.Type: GrantFiled: March 25, 2019Date of Patent: September 15, 2020Assignee: DELPHI TECHNOLOGIES IP LIMITEDInventor: Jack L. Glenn
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Publication number: 20200278309Abstract: A method for assessing a thermal path associated with an integrated circuit includes identifying a heat application mode based on a design type of the integrated circuit. The method also includes measuring a first temperature of at least one thermal sensing device associated with the integrated circuit. The method also includes applying heat to at least a portion of the integrated circuit according to the heat application mode. The method also includes measuring a second temperature of the at least one thermal sensing device. The method also includes determining a difference between the first temperature and the second temperature. The method also includes determining whether a thermal path between the integrated circuit and an associated substrate is sufficient based on a comparison of the difference between the first temperature and the second temperature with a predetermined difference between an initial temperature and a subsequent temperature of the at least one thermal sensing device.Type: ApplicationFiled: March 1, 2019Publication date: September 3, 2020Inventors: Gregg N. Francisco, Kevin M. Gertiser, Jack L. Glenn, Narendra J. Mane, Thomas E. Pritchett, Soumyajit Routh, Kok Wee Yeo
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Patent number: 9559608Abstract: A rectifier circuit includes a MOSFET (M1), and a first Zener diode (D1) or a first Zener-emulator (E1) that emulates the D1. The circuit conducts current in a forward direction from an input to an output, and substantially blocks current in a reverse direction. The M1 is characterized by an on-resistance. A cathode of the D1 or a cathode-contact of the E1 is connected to the input, and the anode of the D1 or an anode-contact of the E1 are connected to the source. The E1 includes a first small-Zener-diode (D11), a first resistor (R11) and a first transistor (M11) interconnected such that the E1 emulates the D1, and is characterized by a Zener-voltage. The Zener-voltage and the on-resistance are selected such that a stored-charge in the body-diode is less than a forward-charge-threshold when current flows in the forward direction, whereby the reverse recover time of the body-diode is reduced.Type: GrantFiled: March 16, 2015Date of Patent: January 31, 2017Assignee: Delphi Technologies, Inc.Inventor: Jack L. Glenn
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Patent number: 9454171Abstract: A controller includes a high-side circuit, a low-side circuit, a level-shift circuit, and a data-validation circuit. The high-side circuit is referenced to an offset-voltage reference that is offset voltage-wise relative to a ground reference of the controller. The low-side circuit is operable to output a control signal for the high-side circuit. The control signal is referenced to the ground reference. The level-shift circuit is configured to output a shifted signal to the high-side circuit that is referenced to the offset-voltage reference and based on the control signal. The data-validation circuit is configured to receive the shifted signal, determine a first value of the shifted signal at a first instant, determine a second value of the shifted signal at a second instant different in time from the first instant, and validate the shifted signal based on a determination that the first value and the second value correspond.Type: GrantFiled: January 7, 2015Date of Patent: September 27, 2016Assignee: Delphi Technologies, Inc.Inventors: Jack L. Glenn, Mark W. Gose, Daniel C. Penrod
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Publication number: 20160276953Abstract: A rectifier circuit includes a MOSFET (M1), and a first Zener diode (D1) or a first Zener-emulator (E1) that emulates the D1. The circuit conducts current in a forward direction from an input to an output, and substantially blocks current in a reverse direction. The M1 is characterized by an on-resistance. A cathode of the D1 or a cathode-contact of the E1 is connected to the input, and the anode of the D1 or an anode-contact of the E1 are connected to the source. The E1 includes a first small-Zener-diode (D11), a first resistor (R11) and a first transistor (M11) interconnected such that the E1 emulates the D1, and is characterized by a Zener-voltage. The Zener-voltage and the on-resistance are selected such that a stored-charge in the body-diode is less than a forward-charge-threshold when current flows in the forward direction, whereby the reverse recover time of the body-diode is reduced.Type: ApplicationFiled: March 16, 2015Publication date: September 22, 2016Inventor: JACK L. GLENN
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Publication number: 20160195885Abstract: A controller includes a high-side circuit, a low-side circuit, a level-shift circuit, and a data-validation circuit. The high-side circuit is referenced to an offset-voltage reference that is offset voltage-wise relative to a ground reference of the controller. The low-side circuit is operable to output a control signal for the high-side circuit. The control signal is referenced to the ground reference. The level-shift circuit is configured to output a shifted signal to the high-side circuit that is referenced to the offset-voltage reference and based on the control signal. The data-validation circuit is configured to receive the shifted signal, determine a first value of the shifted signal at a first instant, determine a second value of the shifted signal at a second instant different in time from the first instant, and validate the shifted signal based on a determination that the first value and the second value correspond.Type: ApplicationFiled: January 7, 2015Publication date: July 7, 2016Inventors: JACK L. GLENN, MARK W. GOSE, DANIEL C. PENROD
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Patent number: 8489357Abstract: An apparatus and method of determining the junction temperature (Tj) and drain-source current (Ids) of a standard FET within a multi-FET module includes a control IC managing one or more 3 terminal standard FETs within the same package, calculating Tj and Tds for one or more FETs in one or more packages, and protecting each FET against short circuit faults while allowing high current transients, such as inrush currents from a lamp load.Type: GrantFiled: July 23, 2009Date of Patent: July 16, 2013Assignee: Delphi Technologies, Inc.Inventors: Jack L. Glenn, Mark A. Gose, Peter A. Laubenstein, Seyed R. Zarabadi
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Publication number: 20110112792Abstract: An apparatus and method of determining the junction temperature (Tj) and drain-source current (Ids) of a standard FET within a multi-FET module includes a control IC managing one or more 3 terminal standard FETs within the same package, calculating Tj and Tds for one or more FETs in one or more packages, and protecting each FET against short circuit faults while allowing high current transients, such as inrush currents from a lamp load.Type: ApplicationFiled: July 23, 2009Publication date: May 12, 2011Applicant: DELPHI TECHNOLOGIES, INC.Inventors: Jack L. Glenn, Mark A. Gose, Peter A. Laubenstein, Seyed R. Zarabadi
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Patent number: 7645627Abstract: A motion sensor in the form of an angular rate sensor and a method of making a sensor are provided and includes a support substrate and a silicon sensing ring supported by the substrate and having a flexive resonance. Drive electrodes apply electrostatic force on the ring to cause the ring to resonate. Sensing electrodes sense a change in capacitance indicative of vibration modes of resonance of the ring so as to sense motion. A plurality of silicon support rings connect the substrate to the ring. The support rings are located at an angle to substantially match a modulus of elasticity of the silicon, such as about 22.5 degrees and 67.5 degrees, with respect to the crystalline orientation of the silicon.Type: GrantFiled: January 24, 2008Date of Patent: January 12, 2010Assignee: Delphi Technologies, Inc.Inventors: John C. Christenson, Dan W. Chilcott, Richard G. Forestal, Jack L. Glenn, Seyed R. Zarabadi
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Patent number: 7619262Abstract: Electrostatic discharge (ESD) protection is provided for an integrated circuit. In an aspect, a dynamic region having doped regions is formed on an epitaxy layer and substrate, and interconnects contact the dynamic region. In an aspect, the dynamic region operates as a back-to-back SCR that snaps back in both positive and negative voltage directions. In an aspect the dynamic region operates as an SCR that snaps back in a positive voltage direction and operates as a simple diode in a negative voltage direction. In another aspect, the dynamic region operates as an SCR that snaps back in a negative voltage direction and operates as a simple diode in a positive voltage direction. ESD protection over an adjustable and wide positive and negative voltage range is provided by varying widths and positioning of various doping regions. Breakdown voltages, critical voltages and critical currents are independently controlled.Type: GrantFiled: November 16, 2006Date of Patent: November 17, 2009Assignee: Delphi Technologies, Inc.Inventors: Jack L. Glenn, Mark W. Gose
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Patent number: 7601990Abstract: Electrostatic discharge (ESD) protection is provided for an integrated circuit. Snap back from a lower initial critical voltage and critical current is provided, as compared to contemporary designs. A dynamic region having doped regions is formed on a substrate, interconnects contacting the dynamic region. The dynamic region includes an Nwell region, a Pwell region and shallow diffusions, defining a PNP region, an NPN region and a voltage Breakdown region. In an aspect, the Nwell region includes a first N+ contact, a first P+ contact and an N+ doped enhancement, while the Pwell region includes a second N+ contact, a second P+ contact and a P+ doped enhancement. The N+ doped enhancement contacts the P+ doped enhancement forming the breakdown voltage region therebetween, in one case forming a buried breakdown voltage junction.Type: GrantFiled: October 25, 2006Date of Patent: October 13, 2009Assignee: Delphi Technologies, Inc.Inventor: Jack L. Glenn
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Publication number: 20090191660Abstract: A motion sensor in the form of an angular rate sensor and a method of making a sensor are provided and includes a support substrate and a silicon sensing ring supported by the substrate and having a flexive resonance. Drive electrodes apply electrostatic force on the ring to cause the ring to resonate. Sensing electrodes sense a change in capacitance indicative of vibration modes of resonance of the ring so as to sense motion. A plurality of silicon support rings connect the substrate to the ring. The support rings are located at an angle to substantially match a modulus of elasticity of the silicon, such as about 22.5 degrees and 67.5 degrees, with respect to the crystalline orientation of the silicon.Type: ApplicationFiled: January 24, 2008Publication date: July 30, 2009Inventors: John C. Christenson, Dan W. Chilcott, Richard G. Forestal, Jack L. Glenn, Seyed R. Zarabadi
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Patent number: 7470955Abstract: An integrated circuit (IC) with negative potential protection includes at least one double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-type substrate. The IC also includes a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket and a first-type+ ring formed through the first-type epitaxial pocket between the second-type+ isolation ring and the DMOS cell.Type: GrantFiled: April 15, 2005Date of Patent: December 30, 2008Assignee: Delphi Technologies, Inc.Inventors: Jack L. Glenn, Troy D. Clear, Mark W. Gose, Doublas B. Osborn, Nicholas T. Campanile
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Publication number: 20080116480Abstract: Electrostatic discharge (ESD) protection is provided for an integrated circuit. In an aspect, a dynamic region having doped regions is formed on an epitaxy layer and substrate, and interconnects contact the dynamic region. In an aspect, the dynamic region operates as a back-to-back SCR that snaps back in both positive and negative voltage directions. In an aspect the dynamic region operates as an SCR that snaps back in a positive voltage direction and operates as a simple diode in a negative voltage direction. In another aspect, the dynamic region operates as an SCR that snaps back in a negative voltage direction and operates as a simple diode in a positive voltage direction. ESD protection over an adjustable and wide positive and negative voltage range is provided by varying widths and positioning of various doping regions. Breakdown voltages, critical voltages and critical currents are independently controlled.Type: ApplicationFiled: November 16, 2006Publication date: May 22, 2008Inventors: Jack L. Glenn, Mark W. Gose
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Publication number: 20080099848Abstract: Electrostatic discharge (ESD) protection is provided for an integrated circuit. Snap back from a lower initial critical voltage and critical current is provided, as compared to contemporary designs. A dynamic region having doped regions is formed on a substrate, interconnects contacting the dynamic region. The dynamic region includes an Nwell region, a Pwell region and shallow diffusions, defining a PNP region, an NPN region and a voltage Breakdown region. In an aspect, the Nwell region includes a first N+ contact, a first P+ contact and an N+ doped enhancement, while the Pwell region includes a second N+ contact, a second P+ contact and a P+ doped enhancement. The N+ doped enhancement contacts the P+ doped enhancement forming the breakdown voltage region therebetween, in one case forming a buried breakdown voltage junction.Type: ApplicationFiled: October 25, 2006Publication date: May 1, 2008Inventor: Jack L. Glenn
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Patent number: 7335954Abstract: An electrostatic discharge (ESD) protection device includes a first-type substrate, a second-type well formed in the substrate and a first-type well formed in the substrate. The second-type well includes a second-type+ region formed between first and second first-type+ regions. The first-type well is formed in the substrate adjacent a first side of the second-type well. The first-type well includes first and second first-type regions with a first-type+ region and a second-type+ region formed between the first and second first-type regions. The second-type+ region of the first-type well is formed between the first-type+ region of the first-type well and the second-type well.Type: GrantFiled: April 20, 2005Date of Patent: February 26, 2008Assignee: Delphi Technolgoies, Inc.Inventors: Jack L. Glenn, Pedro E. Castillo-Borelly