Patents by Inventor Jack Qingsheng Zhao
Jack Qingsheng Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7911006Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.Type: GrantFiled: November 2, 2009Date of Patent: March 22, 2011Assignee: Agere Systems Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Jack Qingsheng Zhao
-
Patent number: 7700432Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region, is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.Type: GrantFiled: January 9, 2009Date of Patent: April 20, 2010Assignee: Agere Systems Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Jack Qingsheng Zhao
-
Publication number: 20100044767Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.Type: ApplicationFiled: November 2, 2009Publication date: February 25, 2010Applicant: Agere Systems Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Jack Qingsheng Zhao
-
Patent number: 7633118Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.Type: GrantFiled: May 31, 2007Date of Patent: December 15, 2009Assignee: Agere Systems Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Jack Qingsheng Zhao
-
Publication number: 20090130810Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region, is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.Type: ApplicationFiled: January 9, 2009Publication date: May 21, 2009Applicant: Agere Systems Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Jack Qingsheng Zhao
-
Patent number: 7491610Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region. is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.Type: GrantFiled: June 1, 2007Date of Patent: February 17, 2009Assignee: Agere Systems Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Jack Qingsheng Zhao
-
Patent number: 7259048Abstract: An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating.Type: GrantFiled: May 19, 2006Date of Patent: August 21, 2007Assignee: Agere Systems, Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Jack Qingsheng Zhao
-
Patent number: 7242056Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.Type: GrantFiled: April 5, 2004Date of Patent: July 10, 2007Assignee: Agere Systems Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, Ross Thomson, Jack Qingsheng Zhao
-
Patent number: 7078280Abstract: An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating.Type: GrantFiled: February 6, 2004Date of Patent: July 18, 2006Assignee: Agere Systems Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Jack Qingsheng Zhao
-
Patent number: 7056783Abstract: An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A third doped region forming a channel of different conductivity type than the first region is positioned over the first region. A fourth doped region of a different conductivity and forming a channel is positioned over the second region. The process of creating the gate structure for each of the two transistors allows for the formation of oxide layers of different thickness between the two transistors. The transistors are therefore capable of operating at different operating voltages (including different threshold voltages). Each transistor further includes fifth and sixth layers positioned respectively over the third and fourth regions and having an opposite conductivity type with respect to the third and fourth regions.Type: GrantFiled: October 14, 2003Date of Patent: June 6, 2006Assignee: Agere Systems Inc.Inventors: Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Samir Chaudhry, Jack Qingsheng Zhao
-
Patent number: 7033877Abstract: An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET. In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a semiconductor layer. A field-effect transistor gate region, including a channel and a gate electrode, is formed over the first source/drain region. A second source/drain region is then formed over the channel having the appropriate conductivity type.Type: GrantFiled: November 26, 2003Date of Patent: April 25, 2006Assignee: Agere Systems Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, Ross Thomson, Jack Qingsheng Zhao
-
Publication number: 20040188737Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region.Type: ApplicationFiled: April 5, 2004Publication date: September 30, 2004Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, Ross Thomson, Jack Qingsheng Zhao
-
Publication number: 20040155264Abstract: An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating.Type: ApplicationFiled: February 6, 2004Publication date: August 12, 2004Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Jack Qingsheng Zhao
-
Patent number: 6759730Abstract: A structure and a process for fabricating a bipolar junction transistor (BJT) that is compatible with the fabrication of a vertical MOSFET is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate, where the substrate includes a buried collector region for the BJT and a source region for the MOSFET. After the at least three layers are formed on the substrate, two windows or trenches are formed in the layers. The first window terminates at the surface of the silicon substrate where the source region has been formed; the second window terminates at the buried collector region. Both windows are then filled with semiconductor material. For the BJT, the bottom portion of the window is filled with material of a conductivity type matching the conductivity of the buried collector, while the upper region of the semiconductor material is doped the opposite conductivity to form the BJT base.Type: GrantFiled: September 18, 2001Date of Patent: July 6, 2004Assignee: Agere Systems Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, Ross Thomson, Jack Qingsheng Zhao
-
Publication number: 20040110345Abstract: An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.Type: ApplicationFiled: November 26, 2003Publication date: June 10, 2004Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, Ross Thomson, Jack Qingsheng Zhao
-
Patent number: 6709904Abstract: An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating.Type: GrantFiled: September 28, 2001Date of Patent: March 23, 2004Assignee: Agere Systems Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Jack Qingsheng Zhao
-
Patent number: 6690040Abstract: A vertical JFET architecture. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is disposed over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.Type: GrantFiled: September 10, 2001Date of Patent: February 10, 2004Assignee: Agere Systems Inc.Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, Ross Thomson, Jack Qingsheng Zhao
-
Patent number: 6686604Abstract: An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A third doped region forming a channel of different conductivity type than the first region is positioned over the first region. A fourth doped region of a different conductivity and forming a channel is positioned over the second region. The process of creating the gate structure for each of the two transistors allows for the formation of oxide layers of different thickness between the two transistors. The transistors are therefore capable of operating at different operating voltages (including different threshold voltages). Each transistor further includes fifth and sixth layers positioned respectively over the third and fourth regions and having an opposite conductivity type with respect to the third and fourth regions.Type: GrantFiled: September 21, 2001Date of Patent: February 3, 2004Assignee: Agere Systems Inc.Inventors: Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Samir Chaudhry, Jack Qingsheng Zhao
-
Publication number: 20030064567Abstract: An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventors: Samir Chaudhry, Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Jack Qingsheng Zhao
-
Publication number: 20030060015Abstract: An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A third doped region forming a channel of different conductivity type than the first region is positioned over the first region. A fourth doped region of a different conductivity and forming a channel is positioned over the second region. The process of creating the gate structure for each of the two transistors allows for the formation of oxide layers of different thickness between the two transistors. The transistors are therefore capable of operating at different operating voltages (including different threshold voltages). Each transistor further includes fifth and sixth layers positioned respectively over the third and fourth regions and having an opposite conductivity type with respect to the third and fourth regions.Type: ApplicationFiled: September 21, 2001Publication date: March 27, 2003Inventors: Paul Arthur Layman, John Russell McMacken, J. Ross Thomson, Samir Chaudhry, Jack Qingsheng Zhao