Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: Described herein are systems, methods, and products utilizing a cache coherent switch on chip. The cache coherent switch on chip may utilize Compute Express Link (CXL) interconnect open standard and allow for multi-host access and the sharing of resources. The cache coherent switch on chip provides for resource sharing between components while independent of a system processor, removing the system processor as a bottleneck. Cache coherent switch on chip may further allow for cache coherency between various different components. Thus, for example, memories, accelerators, and/or other components within the disclose systems may each maintain caches, and the systems and techniques described herein allow for cache coherency between the different components of the system with minimal latency.

Abstract: Methods and structure for utilizing a virtual Expansion ROM. One exemplary embodiment is a management device. The management device includes a memory, a Peripheral Component Interconnect Express (PCIe) link, and a processor. The memory stores Expansion Read-Only Memory (Expansion ROM) boot instructions for a host. The processor identifies devices in a PCIe hierarchy by transmitting PCIe enumeration requests via the PCIe link. The processor also generates a synthetic PCIe hierarchy that includes an added virtual Expansion ROM which is not present in the PCIe hierarchy, and provides responses describing the synthetic PCIe hierarchy to a host. Furthermore, the processor acquires PCIe read requests initiated by the host that are directed to the virtual Expansion ROM, and provides boot instructions to the host from the memory based on the PCIe read requests.

Abstract: Methods and structure for utilizing a virtual Expansion ROM. One exemplary embodiment is a management device. The management device includes a memory, a Peripheral Component Interconnect Express (PCIe) link, and a processor. The memory stores Expansion Read-Only Memory (Expansion ROM) boot instructions for a host. The processor identifies devices in a PCIe hierarchy by transmitting PCIe enumeration requests via the PCIe link. The processor also generates a synthetic PCIe hierarchy that includes an added virtual Expansion ROM which is not present in the PCIe hierarchy, and provides responses describing the synthetic PCIe hierarchy to a host. Furthermore, the processor acquires PCIe read requests initiated by the host that are directed to the virtual Expansion ROM, and provides boot instructions to the host from the memory based on the PCIe read requests.

Abstract: A method of providing unordered packet routing in a multi-path PCIe switch fabric is provided. Fabric egress port congestion is measured and distributed to all ports within a switch and to neighboring switches. An unordered route choice vector is generated by table lookup. The local congestion mask vector identifies which of these choices has local congestion. A next hop masked choice vector generated by table lookup is gated with the next hop congestion mask vectors, received from neighboring switches, to identify the choices that have next hop congestion. Congested choices are excluded by masking. If multiple choices remain at the conclusion of the masking process, then a selection is made by round-robin among the surviving choices. If no choices remain, the selection is made by round robin among the original choices. The final selection is mapped to an egress port on the switch by table lookup.

Abstract: A method of sharing of a function of a device with a plurality of hosts through a PCIe switch is provided. A function on a device is presented to a first host and a second host through the switch. Read and write on the function's register set within the first host and within the second host are captured, thereby enabling a management system of the switch to create a shadow copy of the first host register sets and second host register sets. The creation of sets of shadow queues on the management system is enabled. The first set of shadow queues of the first set of registers is used to direct read and write operations from the first host to the function. The second set of shadow queues of the second set of registers is used to direct read and write operations from the second host to the function.

Abstract: A method of transferring data over a switch fabric with at least one switch with an embedded network class endpoint device is provided. At a device transmit driver a transfer command is received to transfer a message. If the message length is less than a threshold the message is pushed. If the message length is greater than the threshold, the message is pulled.

Abstract: A PCIe switch implements a logical device for use by connected host systems. The logical device is created by logical device enabling software running on a host management system. The logical device is able to consolidate one or more physical devices or may be entirely software-based. Commands from the connected host are processed in the command and response queues in the host and are also reflected in shadow queues stored in the management system. A DMA engine associated with the connected host is set up to automatically trigger on queues in the connected (local) host. Commands are sent to the physical devices to complete the work and a completion signal is sent to the management software and a response to the work is sent directly to the connected host, which is not aware that the logical device is non-existent and is implemented by software in the management system.

Abstract: A method of remote booting over PCI Express using a synthetic remote boot capability is provided. A management host software system intercepts probe requests from a host and provided information required for a remote boot. The management host software system may include expansion ROM information to support different host architectures. A synthetic device booting capability may be shown to a host, including the expansion ROM information. Additional support for DHCP and TFTP may be provided.

Abstract: A method of sharing of a function of a device with a plurality of hosts through a PCIe switch is provided. A function on a device is presented to a first host and a second host through the switch. Read and write on the function's register set within the first host and within the second host are captured, thereby enabling a management system of the switch to create a shadow copy of the first host register sets and second host register sets. The creation of sets of shadow queues on the management system is enabled. The first set of shadow queues of the first set of registers is used to direct read and write operations from the first host to the function. The second set of shadow queues of the second set of registers is used to direct read and write operations from the second host to the function.

Abstract: Tunneled window connections are utilized in a switch fabric to perform programmed input output transfers. The window connections are based on global IDs. A management entity may enforce the tunneled window connections, improving security.

Abstract: A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols.

Abstract: A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols.

Abstract: PCIe is a point-to-point protocol. A PCIe switch fabric has multi-path routing supported by adding an ID routing prefix to a packet entering the switch fabric. The routing is converted within the switch fabric from address routing to ID routing, where the ID is within a Global Space of the switch fabric. Rules are provided to select optimum routes for packets within the switch fabric, including rules for ordered traffic, unordered traffic, and for utilizing congestion feedback. In one implementation a destination lookup table is used to define the ID routing prefix for an incoming packet. The ID routing prefix may be removed at a destination host port of the switch fabric.

Abstract: A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols.

Abstract: In a first embodiment of the present invention, a method for error-correcting in a parallel interconnect transmitting device is provided, the method comprising: detecting a frame transition in a transmission from the transmitting device to a parallel interconnect receiving device; tracking time between the frame transition and a transition of a response signal corresponding to the frame transition received from the receiving device; detecting an error in the transmission; and restarting a portion of the transmission in response to the error, wherein the size of the portion of the transmission to restart is based upon the tracked time between the frame transition and the transition of a response signal corresponding to the frame transition.