Abstract: A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and configured to track a plurality of positions. The positions can include a consumer bank position, a consumer object position, a producer bank position, and a producer object position. The buffer controller is configured to allocate selected ones of the objects from the memory banks to the producer circuit and to the consumer circuit according to the tracked positions and using the hardware locks.

Abstract: A circular buffer architecture includes a memory coupled to a producer circuit and a consumer circuit. The memory is configured to store objects. The memory can include memory banks. The number of the memory banks is less than a number of the objects. The circular buffer can include hardware locks configured to reserve selected ones of the memory banks for use by the producer circuit or the consumer circuit. The circular buffer can include a buffer controller coupled to the memory and configured to track a plurality of positions. The positions can include a consumer bank position, a consumer object position, a producer bank position, and a producer object position. The buffer controller is configured to allocate selected ones of the objects from the memory banks to the producer circuit and to the consumer circuit according to the tracked positions and using the hardware locks.

Abstract: An integrated circuit (IC) can include a decomposer data mover circuit configured to read sub-arrays from array data stored in a source memory; generate metadata headers for the sub-arrays, wherein each metadata header includes location information indicating location of a corresponding sub-array within the array data; create data tiles, wherein each data tile includes a sub-array and a corresponding metadata header; and output the data tiles to compute circuitry within the IC. The IC can include a composer data mover circuit configured to receive processed versions of the data tiles from the compute circuitry; extract valid data regions from the processed versions of the data tiles; and write the valid data regions to a destination memory based on the location information from the metadata headers of the processed versions of the data tiles.

Abstract: A design tool for designing a system includes a display device with a first visualization pane showing a symbolic representation of a connection between a first port and a second port of the system and a second visualization pane showing an unconnected port of the system. A text entry pane on the display device shows a textual definition of the connection. An optional status pane shows a textual log of user-performed actions relating to construction of the system.

Abstract: An integrated circuit includes an auto-bridging architecture including a first phases block that interfaces to a first user block having a first user signal domain. The first phases block converts the first user signal domain to a common signal domain. A second phases block coupled to the first phases block interfaces with a second user block having a second user signal domain. The second phases block converts the second user signal domain to the common signal domain so that the first user block cooperates with the second user block through the auto-bridging architecture of the IC.