Abstract: A method and system for memory management and address translation mapping of pools of logical partitions for BAT and TLB entries in a data processing system is provided. An entry in an address translation buffer is created that is associated with a particular block of virtual memory comprised of a plurality of logical partitions that are grouped in one or more pools of logical partitions, wherein the size of each pool of logical partitions is equal to a preselected page size for real memory, and wherein the entry maps each pool of logical partitions to a page of real memory within a sector of real memory, wherein the size of the sector is a function of the size of the associated block of virtual memory.

Abstract: A method and system for address translation mapping of logical partitions for address translation buffer entries in a data processing system is provided. The method comprises receiving a logical address for a memory reference to a selected logical partition of a plurality of logical partitions of a particular block of virtual memory, wherein the block of virtual memory is divided into the plurality of logical partitions, and wherein the logical address includes a plurality of logical partition selection bits selecting the selected logical partition from among the plurality of logical partitions.