Abstract: Memory access management techniques are described. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. In an embodiment, a load operation may be predicted to not conflict with older pending store operations if a saturation counter corresponding to the load operation is below a threshold value and a maximum rate of mispredictions has not occurred. Other embodiments are also disclosed.

Abstract: A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address.

Abstract: An apparatus and method for prefetching based on fill buffer hits is disclosed. In one embodiment, a processor includes a cache fill buffer and a prefetcher. The cache fill buffer has a number of fill buffer entry locations. Each load entry location is to store a load entry, including an address of data to be loaded into a cache. The prefetcher generates, in response to an instruction needing data from a first address, a request to prefetch data from a second address, if one of the cache fill buffer entries corresponds to the first address.

Abstract: The present invention is directed to an apparatus and method for efficiently calculating an intermediate value between a first end value and a second end value such that the area and time required to implement this operation is minimized. The present invention is also used to efficiently multiply a value by a fraction. A fraction is involved in calculating an intermediate value and also for multiplying by a fraction. When the denominator of the fraction is odd, the binary representation of the blending function, which is used to calculate an intermediate value, exhibits special characteristics. The special characteristics allow the present invention to, among others, avoid the use of multipliers, Which require a large number of gates to implement. This invention exploits this and other special characteristics in order to efficiently implement in hardware the blending function and to efficiently multiply a value by a fraction.

Abstract: An apparatus, system and method for accelerating exchange (XCHG) instructions in a processor using a register alias table (RAT) data array and a content addressable memory (CAM) to handle register renaming. The RAT has at least one read port, at least one write port, and a plurality of address entries. The CAM has at least one read address, at least one write address, and a plurality of swap addresses. A plurality of logical register numbers are used as CAM input addresses to the RAT, and the operation of the CAM is completed in a first phase and a second phase of a clock cycle. The logical register numbers that match a pair of input swap addresses are interchanged.

Abstract: An embodiment of the present invention includes a speculative rename table (SRT), a shadow array, and an update circuit. The SRT stores mapping of frequent and infrequent registers. The frequent registers are frequently modified by instructions dispatched from a processor core. The infrequent registers are infrequently modified by the instructions. The shadow array stores shadow registers. Each of the shadow registers contains a rename state of a corresponding frequent register after a branch instruction. The update circuit transfers contents of the shadow registers to the frequent registers based on a selection condition.

Abstract: An embodiment of the present invention includes a speculative rename table (SRT), a shadow array, and an update circuit. The SRT stores mapping of frequent and infrequent registers. The frequent registers are frequently modified by instructions dispatched from a processor core. The infrequent registers are infrequently modified by the instructions. The shadow array stores shadow registers. Each of the shadow registers contains a rename state of a corresponding frequent register after a branch instruction. The update circuit transfers contents of the shadow registers to the frequent registers based on a selection condition.

Abstract: Some virtual memory systems allow more that one memory page size. To quickly translate virtual page addresses into physical page addresses, a multi-page size translation look-aside buffer is needed. The multi-page size translation look-aside buffer has a virtual address array and a physical address array. The virtual address array has a set of virtual address entries that are compared to a received virtual address. The virtual address array entries have virtual address tag field, a valid bit, and a page size bit. The page size bit defines the size of the memory page and thus defines the number of bits in the virtual address that must be matched with virtual address tag bits in the virtual address array. The valid bit indicates if the entry is valid or not. When a hit is detected in the virtual address array, a corresponding entry in the physical address array is activated. The physical address array comprises a physical page address and a set of page attributes.

Abstract: Some virtual memory systems allow more that one memory page size. To quickly translate virtual page addresses into physical page addresses, a multi-page size translation look-aside buffer is needed. The multi-page size translation look-aside buffer has a virtual address array and a physical address array. The virtual address array has a set of virtual address entries that are compared to a received virtual address. The virtual address array entries have virtual address tag field, a valid bit, and a page size bit. The page size bit defines the size of the memory page and thus defines the number of bits in the virtual address that must be matched with virtual address tag bits in the virtual address array. The valid bit indicates if the entry is valid or not. When a hit is detected in the virtual address array, a corresponding entry in the physical address array is activated. The physical address array comprises a physical page address and a set of page attributes.