Patents by Inventor Jacob L. Moilanen

Jacob L. Moilanen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8701111
    Abstract: Methods and arrangements to assign locks to threads are discussed. Embodiments include transformations, code, state machines or other logic to assign locks to threads. Embodiments may include setting a window of time at the end of a time slice of a thread. The embodiment may also involve prohibiting the thread from acquiring a lock during the window of time, based upon determining that the thread is within the window of time and determining that the thread does not hold any locks. Other embodiments include an apparatus to assign locks to threads and a computer program product to assign locks to threads.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: April 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nathan Fontenot, Jacob L. Moilanen, Joel H. Schopp, Michael T. Strosaker, Mark W. VanderWiele
  • Patent number: 8656405
    Abstract: A mechanism is provided for scheduling tasks across multiple processor units of differing capacity. In a multiple processor unit system with processor units of disparate speeds, it is advantageous to have the most processing-intensive tasks run on the processor units with the highest capacity. All tasks are initially scheduled on the lowest capacity processor units. Because processor units with higher capacity are more likely to have idle time, these higher capacity processor units may pull one or more tasks onto themselves from the same or lower capacity processor units. A processor unit will attempt to pull tasks that utilize a larger percentage of the timeslice. When a higher capacity processor unit is overloaded or near capacity, the higher capacity processor unit may push tasks to processor units with the same or lower capacity. A processor unit will attempt to push tasks that utilize a smaller percentage of the timeslice.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nathan D. Fontenot, Jacob L. Moilanen, Joel H. Schopp, Michael T. Strosaker
  • Patent number: 8312105
    Abstract: Provided is a method for displaying information such as lists of data, files and icons in a window of a graphical user interface (GUI). Unlike a typical display methodology, which arranges items in a “machine-dependent” sorting order, the disclosed technology provides a “natural” sorting order. The list, or names associated with the files or icons are incorporated into a query and the query is transmitted to a web service. The web service parses the query to determine a natural order appropriate to the material represented by the list, files, or icons rearranges the list, files or icons into the natural order and returns a response to the originator of the query. The operating system or GUI that originated the query receives the response, parses the response and displays the list, files or icons in the corresponding natural order.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Michael N. Abernethy, Jr., Travis M. Grigsby, Jacob L. Moilanen, Nazgol Sedghi
  • Patent number: 8291397
    Abstract: A mechanism and functionality are provided for generating and using compiler optimized function variants. These variants may be used, for example, in situations where return values of functions called by code are not thereafter used by the code calling the functions. In particular, for a function called by computer code, at least two variants for the function may be generated. A function call, for calling the function, within original computer code may be analyzed to determine which variant of the at least two variants to use for the function call. The function call may be modified in the original computer code, to generate modified computer code, based on results of the analysis identifying which variant of the at least two variants to use for the function call.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Manish Ahuja, Nathan D. Fontenot, Jacob L. Moilanen, Joel H. Schopp, Michael T. Strosaker
  • Patent number: 8230425
    Abstract: Methods and arrangements of assigning tasks to processors are discussed. Embodiments include transformations, code, state machines or other logic to detect an attempt to execute an instruction of a task on a processor not supporting the instruction (non-supporting processor). The method may involve selecting a processor supporting the instruction (supporting physical processor). In many embodiments, the method may include storing data about the attempt to execute the instruction and, based upon the data, making another assignment of the task to a physical processor supporting the instruction. In some embodiments, the method may include representing the instruction set of a virtual processor as the union of the instruction sets of the physical processors comprising the virtual processor and assigning a task to the virtual processor based upon the representing.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: July 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Manish Ahuja, Nathan Fontenot, Jacob L. Moilanen, Joel H. Schopp, Michael T. Strosaker
  • Patent number: 8140817
    Abstract: A partitioned NUMA machine is managed to dynamically transform its partition layout state based on NUMA considerations. The NUMA machine includes two or more NUMA nodes that are operatively interconnected by one or more internodal communication links. Each node includes one or more CPUs and associated memory circuitry. Two or more logical partitions each comprise at a CPU and memory circuit allocation on at least one NUMA node. Each partition respectively runs at least one associated data processing application. The partitions are dynamically managed at runtime to transform the distributed data processing machine from a first partition layout state to a second partition layout state that is optimized for the data processing applications according to whether a given partition will most efficiently execute within a single NUMA node or by spanning across a node boundary. The optimization is based on access latency and bandwidth in the NUMA machine.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joel H. Schopp, Jacob L. Moilanen, Nathan D. Fontenot, Michael T. Strosaker, Manish Ahuja
  • Patent number: 7870370
    Abstract: Methods, apparatus, and products for determining thermal characteristics of instruction sets comprising one or more computer program instructions executed by a computer processor are disclosed that include tracking, in a performance counter, a number of classes of instructions run during execution of a plurality of instruction sets; identifying, for each instruction set, from the performance counter, a number of each class of instructions run during execution of the instruction set; and ranking the instruction sets in dependence upon the number of each class of instructions run during execution of each instruction set and a profile of thermal characteristics of classes of instructions.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Nathan D. Fontenot, Jacob L. Moilanen, Joel H. Schopp, Michael T. Strosaker
  • Publication number: 20100274851
    Abstract: Provided is a method for displaying information such as lists of data, files and icons in a window of a graphical user interface (GUI). Unlike a typical display methodology, which arranges items in a “machine-dependent” sorting order, the disclosed technology provides a “natural” sorting order. The list, or names associated with the files or icons are incorporated into a query and the query is transmitted to a web service. The web service parses the query to determine a natural order appropriate to the material represented by the list, files, or icons rearranges the list, files or icons into the natural order and returns a response to the originator of the query. The operating system or GUI that originated the query receives the response, parses the response and displays the list, files or icons in the corresponding natural order.
    Type: Application
    Filed: April 28, 2009
    Publication date: October 28, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael N. Abernethy, JR., Travis M. Grigsby, Jacob L. Moilanen, Nazgol Sedghi
  • Publication number: 20100217949
    Abstract: A partitioned NUMA machine is managed to dynamically transform its partition layout state based on NUMA considerations. The NUMA machine includes two or more NUMA nodes that are operatively interconnected by one or more internodal communication links. Each node includes one or more CPUs and associated memory circuitry. Two or more logical partitions each comprise at a CPU and memory circuit allocation on at least one NUMA node. Each partition respectively runs at least one associated data processing application. The partitions are dynamically managed at runtime to transform the distributed data processing machine from a first partition layout state to a second partition layout state that is optimized for the data processing applications according to whether a given partition will most efficiently execute within a single NUMA node or by spanning across a node boundary. The optimization is based on access latency and bandwidth in the NUMA machine.
    Type: Application
    Filed: February 24, 2009
    Publication date: August 26, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joel H. Schopp, Jacob L. Moilanen, Nathan D. Fontenot, Michael T. Strosaker, Manish Ahuja
  • Publication number: 20100011360
    Abstract: Methods and arrangements to assign locks to threads are discussed. Embodiments include transformations, code, state machines or other logic to assign locks to threads. Embodiments may include setting a window of time at the end of a time slice of a thread. The embodiment may also involve prohibiting the thread from acquiring a lock during the window of time, based upon determining that the thread is within the window of time and determining that the thread does not hold any locks. Other embodiments include an apparatus to assign locks to threads and a computer program product to assign locks to threads.
    Type: Application
    Filed: July 9, 2008
    Publication date: January 14, 2010
    Applicant: International Business Machines Corporation
    Inventors: Nathan Fontenot, Jacob L. Moilanen, Joel H. Schopp, Michael T. Strosaker, Mark W. VanderWiele
  • Publication number: 20090254893
    Abstract: A mechanism and functionality are provided for generating and using compiler optimized function variants. These variants may be used, for example, in situations where return values of functions called by code are not thereafter used by the code calling the functions. In particular, for a function called by computer code, at least two variants for the function may be generated. A function call, for calling the function, within original computer code may be analyzed to determine which variant of the at least two variants to use for the function call. The function call may be modified in the original computer code, to generate modified computer code, based on results of the analysis identifying which variant of the at least two variants to use for the function call.
    Type: Application
    Filed: April 2, 2008
    Publication date: October 8, 2009
    Applicant: International Business Machines Corporation
    Inventors: Manish Ahuja, Nathan D. Fontenot, Jacob L. Moilanen, Joel H. Schopp, Michael T. Strosaker
  • Publication number: 20090164765
    Abstract: Methods, apparatus, and products for determining thermal characteristics of instruction sets comprising one or more computer program instructions executed by a computer processor are disclosed that include tracking, in a performance counter, a number of classes of instructions run during execution of a plurality of instruction sets; identifying, for each instruction set, from the performance counter, a number of each class of instructions run during execution of the instruction set; and ranking the instruction sets in dependence upon the number of each class of instructions run during execution of each instruction set and a profile of thermal characteristics of classes of instructions.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 25, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nathan D. Fontenot, Jacob L. Moilanen, Joel H. Schopp, Michael T. Strosaker
  • Patent number: 7530060
    Abstract: Methods and computer program products for providing warnings and hints related to coding conventions using a coding style definition are provided. A source code is received, and a coding style definition is read. The source code is parsed to determine whether the source code adheres to the conventions in the coding style definition. Warnings are provided to indicate where the source code deviates from the coding style definition, if the source code fails to adhere to the conventions in the coding style definition. If the source code correctly adheres to the conventions in the coding style, hints can be provided to the compiler and linker so that they can optimize effectively using information that the compiler and linker would not normally have.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: May 5, 2009
    Assignee: International Business Machines Corporation
    Inventors: Nathan Fontenot, Jacob L. Moilanen, Joel H. Schopp, Michael T. Strosaker
  • Publication number: 20090037911
    Abstract: Methods and arrangements of assigning tasks to processors are discussed. Embodiments include transformations, code, state machines or other logic to detect an attempt to execute an instruction of a task on a processor not supporting the instruction (non-supporting processor). The method may involve selecting a processor supporting the instruction (supporting physical processor). In many embodiments, the method may include storing data about the attempt to execute the instruction and, based upon the data, making another assignment of the task to a physical processor supporting the instruction. In some embodiments, the method may include representing the instruction set of a virtual processor as the union of the instruction sets of the physical processors comprising the virtual processor and assigning a task to the virtual processor based upon the representing.
    Type: Application
    Filed: July 30, 2007
    Publication date: February 5, 2009
    Inventors: Manish Ahuja, Nathan Fontenot, Jacob L. Moilanen, Joel H. Schopp, Michael T. Strosaker
  • Publication number: 20080320487
    Abstract: A mechanism is provided for scheduling tasks across multiple processor units of differing capacity. In a multiple processor unit system with processor units of disparate speeds, it is advantageous to have the most processing-intensive tasks run on the processor units with the highest capacity. All tasks are initially scheduled on the lowest capacity processor units. Because processor units with higher capacity are more likely to have idle time, these higher capacity processor units may pull one or more tasks onto themselves from the same or lower capacity processor units. A processor unit will attempt to pull tasks that utilize a larger percentage of the timeslice. When a higher capacity processor unit is overloaded or near capacity, the higher capacity processor unit may push tasks to processor units with the same or lower capacity. A processor unit will attempt to push tasks that utilize a smaller percentage of the timeslice.
    Type: Application
    Filed: June 25, 2007
    Publication date: December 25, 2008
    Inventors: Nathan D. Fontenot, Jacob L. Moilanen, Joel H. Schopp, Michael T. Strosaker
  • Publication number: 20080126819
    Abstract: A method for dynamic redundancy of processing units. The method includes defining at least one of, (i) an instruction, and (ii) a call, to idle a first processing unit. Both the instruction and the call are blocking operations that shall not return while a second processing unit and the first processing unit are paired together. The method further includes executing at least one of, (i) the defined instruction, and (ii) the call, and temporarily stopping the paired processing unit. Then, the method proceeds by synchronizing the state and enabling the redundant processor execution. Afterwards, the method includes restarting execution of both processing units together.
    Type: Application
    Filed: November 29, 2006
    Publication date: May 29, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jacob L. Moilanen, Joel H. Schopp, Michael T. Strosaker