Patents by Inventor Jacob Schmier
Jacob Schmier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11726717Abstract: Aspects of a storage device including a memory and a controller are provided which allow for detection of dropped commands based on a die status (ready/busy status) of a command received from a host device. The memory may include dies controlled by chip-enables (CE). After selecting a die using CE, the controller waits between a minimum and maximum time after receiving the command to query the die status, where the minimum time is the time by which the command is expected to begin execution and the maximum time is the shortest time by which the command is expected to complete execution. The controller queries the die status after waiting the time period. If the die status is ready when it should have read busy, the controller detects that the command associated with the data is dropped and requests the host device to reissue the command.Type: GrantFiled: September 30, 2021Date of Patent: August 15, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Robert Ellis, Kevin O'Toole, Jacob Schmier
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Patent number: 11640243Abstract: A method and apparatus is disclosed for using supervised learning with closed loop feedback to improvement of output consistency for memory arrangements, such as a solid state drive.Type: GrantFiled: November 30, 2020Date of Patent: May 2, 2023Assignee: Western Digital Technologies, Inc.Inventors: Rushang Karia, Mervyn Wongso, Jacob Schmier, Kevin Corbin, Lakshmana Rao Chintada
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Patent number: 11294819Abstract: Aspects of a storage device including a memory and a controller are provided which prevent retransmissions of set features commands with identical read voltage threshold offsets for the same die. When the controller receives a first read command for data stored in the memory, the controller identifies a first parameter to modify a first read threshold, and executes a first set features command for modifying the read threshold based on the first parameter. Subsequently, when the controller receives a second read command from the host device for data stored in the memory, the controller identifies a second parameter to modify a second read threshold, and determines whether the first and second parameters are the same. If the parameters are the same, the controller refrains from executing a second set features command for modifying the second read threshold. Thus, the read latency of the storage device may be reduced.Type: GrantFiled: March 31, 2020Date of Patent: April 5, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Robert Ellis, Kevin O'Toole, Jacob Schmier, Todd Lindberg, Atif Hussain, Venugopal Garuda
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Publication number: 20220019382Abstract: Aspects of a storage device including a memory and a controller are provided which allow for detection of dropped commands based on a die status (ready/busy status) of a command received from a host device. The memory may include dies controlled by chip-enables (CE). After selecting a die using CE, the controller waits between a minimum and maximum time after receiving the command to query the die status, where the minimum time is the time by which the command is expected to begin execution and the maximum time is the shortest time by which the command is expected to complete execution. The controller queries the die status after waiting the time period. If the die status is ready when it should have read busy, the controller detects that the command associated with the data is dropped and requests the host device to reissue the command.Type: ApplicationFiled: September 30, 2021Publication date: January 20, 2022Inventors: Robert ELLIS, Kevin O'TOOLE, Jacob Schmier
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Patent number: 11150841Abstract: Aspects of a storage device including a memory and a controller are provided which allow for detection of dropped commands based on a die status (ready/busy status) of a command received from a host device. The memory may include dies controlled by chip-enables (CE). After selecting a die using CE, the controller waits between a minimum and maximum time after receiving the command to query the die status, where the minimum time is the time by which the command is expected to begin execution and the maximum time is the shortest time by which the command is expected to complete execution. The controller queries the die status after waiting the time period. If the die status is ready when it should have read busy, the controller detects that the command associated with the data is dropped and requests the host device to reissue the command.Type: GrantFiled: February 10, 2020Date of Patent: October 19, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Robert Ellis, Kevin O'Toole, Jacob Schmier
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Publication number: 20210303474Abstract: Aspects of a storage device including a memory and a controller are provided which prevent retransmissions of set features commands with identical read voltage threshold offsets for the same die. When the controller receives a first read command for data stored in the memory, the controller identifies a first parameter to modify a first read threshold, and executes a first set features command for modifying the read threshold based on the first parameter. Subsequently, when the controller receives a second read command from the host device for data stored in the memory, the controller identifies a second parameter to modify a second read threshold, and determines whether the first and second parameters are the same. If the parameters are the same, the controller refrains from executing a second set features command for modifying the second read threshold. Thus, the read latency of the storage device may be reduced.Type: ApplicationFiled: March 31, 2020Publication date: September 30, 2021Inventors: Robert Ellis, Kevin O'Toole, Jacob Schmier, Todd Lindberg, Atif Hussain, Venugopal Garuda
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Publication number: 20210247931Abstract: Aspects of a storage device including a memory and a controller are provided which allow for detection of dropped commands based on a die status (ready/busy status) of a command received from a host device. The memory may include dies controlled by chip-enables (CE). After selecting a die using CE, the controller waits between a minimum and maximum time after receiving the command to query the die status, where the minimum time is the time by which the command is expected to begin execution and the maximum time is the shortest time by which the command is expected to complete execution. The controller queries the die status after waiting the time period. If the die status is ready when it should have read busy, the controller detects that the command associated with the data is dropped and requests the host device to reissue the command.Type: ApplicationFiled: February 10, 2020Publication date: August 12, 2021Inventors: Robert Ellis, Kevin O'Toole, Jacob Schmier
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Patent number: 10956083Abstract: A non-volatile memory (NVM) system receives host requests that each specify a memory operation to be performed by the NVM system, the specified memory operations including read operations and write operations, and performs a set of operations for each memory operation specified by a received host request. The set of operations performed for each such memory operation include: initiating performance the memory operation; determining a throttle interval for the memory operation in accordance with at least a first factor, corresponding to available space in a write cache of the non-volatile memory system, and a second factor, corresponding to a metric corresponding to prevalence of write operations in the memory operations specified by the received host requests; and returning to the host system a response associated with the memory operation at a time no earlier than a start time associated with the memory operation plus the determined throttle interval.Type: GrantFiled: August 31, 2017Date of Patent: March 23, 2021Assignee: Western Digital Technologies, Inc.Inventors: Mervyn Wongso, Rushang Karia, Edoardo Daelli, Jacob Schmier, Kevin Corbin, Lakshmana Rao Chintada
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Publication number: 20210081106Abstract: A method and apparatus is disclosed for using supervised learning with closed loop feedback to improvement of output consistency for memory arrangements, such as a solid state drive.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Inventors: Rushang KARIA, Mervyn WONGSO, Jacob SCHMIER, Kevin CORBIN, Lakshmana Rao CHINTADA
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Patent number: 10896724Abstract: A memory system comprises a plurality of memory dies and a controller (or other control circuit) connected to the memory dies. To reduce the time it takes for the memory system to program data and make that programmed data available for reading by a host (or other entity), as well as persistently store the data in a compact manner that efficiently uses space in the memory system, the data is concurrently programmed as single bit per memory cell (fast programming) and multiple bits per memory cell (compact storage). To accomplish this programming strategy, the controller concurrently transfers data to be programmed to a first memory die and a second memory die. The transferred data is programmed in the first memory die at a single bit per memory cell and in the second memory die at multiple bits per memory cell.Type: GrantFiled: December 18, 2018Date of Patent: January 19, 2021Assignee: Western Digital Technologies, Inc.Inventors: Jacob Schmier, Todd Lindberg, Robert Ellis
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Patent number: 10877667Abstract: A method and apparatus is disclosed for using supervised learning with closed loop feedback to improvement of output consistency for memory arrangements, such as a solid state drive.Type: GrantFiled: April 6, 2018Date of Patent: December 29, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Rushang Karia, Mervyn Wongso, Jacob Schmier, Kevin Corbin, Lakshmana Rao Chintada
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Publication number: 20200194065Abstract: A memory system comprises a plurality of memory dies and a controller (or other control circuit) connected to the memory dies. To reduce the time it takes for the memory system to program data and make that programmed data available for reading by a host (or other entity), as well as persistently store the data in a compact manner that efficiently uses space in the memory system, the data is concurrently programmed as single bit per memory cell (fast programming) and multiple bits per memory cell (compact storage). To accomplish this programming strategy, the controller concurrently transfers data to be programmed to a first memory die and a second memory die. The transferred data is programmed in the first memory die at a single bit per memory cell and in the second memory die at multiple bits per memory cell.Type: ApplicationFiled: December 18, 2018Publication date: June 18, 2020Applicant: Western Digital Technologies, Inc.Inventors: Jacob Schmier, Todd Lindberg, Robert Ellis
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Publication number: 20180329626Abstract: A method and apparatus is disclosed for using supervised learning with closed loop feedback to improvement of output consistency for memory arrangements, such as a solid state drive.Type: ApplicationFiled: April 6, 2018Publication date: November 15, 2018Inventors: Rushang KARIA, Mervyn WONGSO, Jacob SCHMIER, Kevin CORBIN, Lakshmana Rao CHINTADA
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Publication number: 20180173464Abstract: A non-volatile memory (NVM) system receives host requests that each specify a memory operation to be performed by the NVM system, the specified memory operations including read operations and write operations, and performs a set of operations for each memory operation specified by a received host request. The set of operations performed for each such memory operation include: initiating performance the memory operation; determining a throttle interval for the memory operation in accordance with at least a first factor, corresponding to available space in a write cache of the non-volatile memory system, and a second factor, corresponding to a metric corresponding to prevalence of write operations in the memory operations specified by the received host requests; and returning to the host system a response associated with the memory operation at a time no earlier than a start time associated with the memory operation plus the determined throttle interval.Type: ApplicationFiled: August 31, 2017Publication date: June 21, 2018Applicant: Western Digital Technologies, Inc.Inventors: Mervyn Wongso, Rushang Karia, Edoardo DaeIli, Jacob Schmier, Kevin Corbin, Lakshmana Rao Chintada
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Patent number: 9183137Abstract: A method of operation of a storage control system includes: calculating a throttle threshold; identifying a detection point based on the throttle threshold; and calculating a number of write/erase cycles based on the detection point and the throttle threshold for writing a memory device.Type: GrantFiled: February 27, 2013Date of Patent: November 10, 2015Assignee: SMART STORAGE SYSTEMS, INC.Inventors: Jacob Schmier, Mark Dancho, James M Higgins, Ryan Jones, Robert W Ellis
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Patent number: 9092370Abstract: The various implementations described herein include systems, methods and/or devices used to enable power failure tolerant cryptographic erasure in a storage device having a first encryption key established as a current encryption key. The method includes performing a set of first stage operations including selecting first and second sets of memory blocks and obtaining a second encryption key. The method includes performing a set of second stage operations including storing, in the first set of memory blocks, first and second sets of metadata, encrypted using the second encryption key. The method includes performing a set of third stage operations, including storing, in the second set of memory blocks, the second set of metadata encrypted using the second encryption key. The method includes setting the second encryption key as the current encryption key for the plurality of memory blocks.Type: GrantFiled: December 19, 2013Date of Patent: July 28, 2015Assignee: SANDISK ENTERPRISE IP LLCInventors: Jacob Schmier, Mark Dancho, Ryan Jones
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Publication number: 20150154121Abstract: The various implementations described herein include systems, methods and/or devices used to enable power failure tolerant cryptographic erasure in a storage device having a first encryption key established as a current encryption key. The method includes performing a set of first stage operations including selecting first and second sets of memory blocks and obtaining a second encryption key. The method includes performing a set of second stage operations including storing, in the first set of memory blocks, first and second sets of metadata, encrypted using the second encryption key. The method includes performing a set of third stage operations, including storing, in the second set of memory blocks, the second set of metadata encrypted using the second encryption key. The method includes setting the second encryption key as the current encryption key for the plurality of memory blocks.Type: ApplicationFiled: December 19, 2013Publication date: June 4, 2015Applicant: SanDisk Enterprise IP LLCInventors: Jacob Schmier, Mark Dancho, Ryan Jones
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Publication number: 20140244899Abstract: A method of operation of a storage control system includes: calculating a throttle threshold; identifying a detection point based on the throttle threshold; and calculating a number of write/erase cycles based on the detection point and the throttle threshold for writing a memory device.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: SMART STORAGE SYSTEMS, INC.Inventors: Jacob Schmier, Mark Dancho, James M Higgins, Ryan Jones, Robert W Ellis
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Patent number: 8356071Abstract: A system and method for providing a presentation to a display client. In one illustrative embodiment, the display client can be an IP phone. The presentation can be provided over a network from a central location without requiring end user action at the IP phone. The presentation can be modified for optimal display based on the capabilities of the specific IP phone without affecting the quality of the presentation for other device types. The devices capable of viewing the presentation can include desk display telephones, cellular telephones, smart phones, portable computers, PCs, and possibly other appropriate network-enabled devices. Centrally controlled presentations can be pushed to an individual device, group of devices, and/or all devices site-wide. In some applications, the display client can be used to provide user selections in response to the provided presentation.Type: GrantFiled: May 14, 2010Date of Patent: January 15, 2013Assignee: Mitel Networks CorporationInventor: Jacob Schmier
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Publication number: 20110282933Abstract: A system and method for providing a presentation to a display client. In one illustrative embodiment, the display client can be an IP phone. The presentation can be provided over a network from a central location without requiring end user action at the IP phone. The presentation can be modified for optimal display based on the capabilities of the specific IP phone without affecting the quality of the presentation for other device types. The devices capable of viewing the presentation can include desk display telephones, cellular telephones, smart phones, portable computers, PCs, and possibly other appropriate network-enabled devices. Centrally controlled presentations can be pushed to an individual device, group of devices, and/or all devices site-wide. In some applications, the display client can be used to provide user selections in response to the provided presentation.Type: ApplicationFiled: May 14, 2010Publication date: November 17, 2011Inventor: Jacob Schmier