Abstract: A method of fabricating a complementary metal-oxide-semiconductor device is provided. The method includes forming a work function material layer segment on a gate dielectric layer over a first vertical fin and a bottom spacer layer on an n-type bottom source/drain adjoining the first vertical fin on a first region of a substrate, wherein the gate dielectric layer is also over a second vertical fin, bottom spacer layer on a p-type bottom source/drain adjoining the second vertical fin on a second region. The method further includes heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value, forming a second work function material layer on the modified work function material layer segment and the gate dielectric layer on the second vertical fin, and growing a top source/drain on each of the vertical fins.

Abstract: Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.

Abstract: Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.

Abstract: A method of fabricating a complementary metal-oxide-semiconductor device is provided. The method includes forming a work function material layer segment on a gate dielectric layer over a first vertical fin and a bottom spacer layer on an n-type bottom source/drain adjoining the first vertical fin on a first region of a substrate, wherein the gate dielectric layer is also over a second vertical fin, bottom spacer layer on a p-type bottom source/drain adjoining the second vertical fin on a second region. The method further includes heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value, forming a second work function material layer on the modified work function material layer segment and the gate dielectric layer on the second vertical fin, and growing a top source/drain on each of the vertical fins.

Abstract: A method of fabricating a complementary metal-oxide-semiconductor device is provided. The method includes forming a work function material layer segment on a gate dielectric layer over a first vertical fin and a bottom spacer layer on an n-type bottom source/drain adjoining the first vertical fin on a first region of a substrate, wherein the gate dielectric layer is also over a second vertical fin, bottom spacer layer on a p-type bottom source/drain adjoining the second vertical fin on a second region. The method further includes heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value, forming a second work function material layer on the modified work function material layer segment and the gate dielectric layer on the second vertical fin, and growing a top source/drain on each of the vertical fins.

Abstract: A method of fabricating a complementary metal-oxide-semiconductor device is provided. The method includes forming a work function material layer segment on a gate dielectric layer over a first vertical fin and a bottom spacer layer on an n-type bottom source/drain adjoining the first vertical fin on a first region of a substrate, wherein the gate dielectric layer is also over a second vertical fin, bottom spacer layer on a p-type bottom source/drain adjoining the second vertical fin on a second region. The method further includes heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value, forming a second work function material layer on the modified work function material layer segment and the gate dielectric layer on the second vertical fin, and growing a top source/drain on each of the vertical fins.

Abstract: Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.

Abstract: A trigger has an upper board and a lower board. The lower board is detachably mounted on the upper board and has an open slot and an elongate board. The open slot is formed through an end of the lower board, and the elongate board is formed on the middle of the open slot and extends to the end of the lower board. The free end of the elongate board is bent perpendicularly to the elongate board. The door track with the trigger includes two installation boards, and two ribs are formed on the two installation boards respectively and extend toward each other. The upper board is mounted on the top surfaces of the ribs of the installation boards, and the lower board is mounted on the bottom surfaces of the ribs. When the sliding door collides with the trigger, the trigger can be deformed and prevents the slider of the sliding door from being restricted by the trigger.

Abstract: A trigger has an upper board and a lower board. The lower board is detachably mounted on the upper board and has an open slot and an elongate board. The open slot is formed through an end of the lower board, and the elongate board is formed on the middle of the open slot and extends to the end of the lower board. The free end of the elongate board is bent perpendicularly to the elongate board. The door track with the trigger includes two installation boards, and two ribs are formed on the two installation boards respectively and extend toward each other. The upper board is mounted on the top surfaces of the ribs of the installation boards, and the lower board is mounted on the bottom surfaces of the ribs. When the sliding door collides with the trigger, the trigger can be deformed and prevents the slider of the sliding door from being restricted by the trigger.

Abstract: A two-way soft closing device is mounted in a sliding door and has a sliding door track, two soft closing activation triggers, two roller carriers and a soft closing device. The sliding door track is an elongated member. The soft closing activation triggers are mounted movably in two ends of the sliding door track respectively. The roller carriers are mounted slidably in the sliding door track and are spaced apart at an interval. The soft closing device is mounted in the sliding door track, is located between the roller carriers and is mounted firmly in one of the roller carriers. Therefore, the soft closing device absorbs a collision between a sliding door plate and a doorframe when the sliding door is opened or is closed. Meanwhile, the two-way soft closing device eliminates noise coming from the collision and prevents an elder or a little child from being hit by the sliding door plate.

Abstract: A two-way soft closing device is mounted in a sliding door and has a sliding door track, two soft closing activation triggers, two roller carriers and a soft closing device. The sliding door track is an elongated member. The soft closing activation triggers are mounted movably in two ends of the sliding door track respectively. The roller carriers are mounted slidably in the sliding door track and are spaced apart at an interval. The soft closing device is mounted in the sliding door track, is located between the roller carriers and is mounted firmly in one of the roller carriers. Therefore, the soft closing device absorbs a collision between a sliding door plate and a doorframe when the sliding door is opened or is closed. Meanwhile, the two-way soft closing device eliminates noise coming from the collision and prevents an elder or a little child from hit by the sliding doorplate.

Abstract: As disclosed herein, a method is provided for simultaneously patterning features having a first width in a first portion such as a logic portion of an integrated circuit, and having a second width in a second portion such as an array portion of an integrated circuit. The method includes depositing a feature layer over a substrate and a hardmask material layer thereover. Photoresist patterns are then formed in the first and second portions with a critical dimension mask, and are then used to etch the hardmask material layer into hardmask patterns. Sidewall spacers are provided on sidewalls of the hardmask patterns in the second portion. Then, the feature layer is simultaneously etched in both first and second portions, using the hardmask patterns in the first portion to define features having a first width, and using the hardmask patterns and the sidewall spacers in the second portion to define features having a second width.

Abstract: As disclosed herein, a method is provided for simultaneously patterning features having a first width in a first portion such as a logic portion of an integrated circuit, and having a second width in a second portion such as an array portion of an integrated circuit. The method includes depositing a feature layer over a substrate and a hardmask material layer thereover. Photoresist patterns are then formed in the first and second portions with a critical dimension mask, and are then used to etch the hardmask material layer into hardmask patterns. Sidewall spacers are provided on sidewalls of the hardmask patterns in the second portion. Then, the feature layer is simultaneously etched in both first and second portions, using the hardmask patterns in the first portion to define features having a first width, and using the hardmask patterns and the sidewall spacers in the second portion to define features having a second width.