Abstract: A COFDM demodulator including a fast Fourier transform circuit analyzing a received signal in a window corresponding to one symbol, each symbol carrying several phase and amplitude modulated carriers, some of which are shifted in frequency in a predetermined way from one symbol to the next one to form pilots; a bidimensional filter for interpolating, from anchors corresponding to the pilots such as received from several consecutive symbols, the distortion undergone by each carrier; and a circuit for correcting the shifting of the window with respect to an optimal position. The demodulator includes a circuit for correcting each distortion according to window shifting corrections performed respectively for the symbol associated with the distortion and for the symbols associated with the anchors used to interpolate the distortion.

Abstract: A method and a device for estimating a first value of a signal formed of a series of values corresponding either to the first value or to a second value equal to the opposite of the first value, where the signal can take values other than the first and second values due to noise.

Abstract: A process of correction of the spectral inversion for a receiver in a digital communication system: the process allows the reception in the receiver of a training sequence presumably known according to a modulation of type ?/2 BPSK or MDP2. The process includes the following steps: Demodulating of the training sequence; Calculating of the differential correlation on a set of N received samples (Rn) and presumably sent (Sn) to generate a result; Using the result to detect the beginning of the frame and to order a spectral inversion in the chain of reception of the aforementioned receiver before launching the detection of the beginning of the frame. A receiver to process automatically the spectral inversion is also described.

Abstract: A demodulation circuit for demodulating a received signal including carriers in quadrature modulated by digital signals and/or in which the processing is performed on two carriers in quadrature. The circuit includes a demodulator, an analog-to-digital converter, a correcting circuit, and a derotator. The correcting circuit provides signals to the derotator based on the derotator output signals and on signals provided by the analog-to-digital converter.

Abstract: A device for providing a digital error signal, for a timing correction loop of a digital demodulator for digital transmission by phase modulation or amplitude and phase modulation, the device successively receiving pairs of digital signals representative of the components of complex signals, and having circuitry for providing a difference signal representative of the difference between the modulus of the complex signal corresponding to the last received pair of digital signals and the modulus of the complex signal corresponding to the previously-received pair of digital signals; circuitry for providing a weighting factor which depends on the angle between the complex signal corresponding to the last received pair of digital signals and the complex signal corresponding to the previously-received pair of digital signals; and circuitry for providing the error signal proportional to the product of the difference signal and of the weighting factor.

Abstract: A method and a device for determining, in a signal, a value of the frequency of a carrier and a value of the frequency of symbols carried by the carrier. A band of the signal is analyzed at three points and the relations between the powers at these points enable determining values of the carrier frequency and of the symbol frequency.

Abstract: A process for receiving a composite signal transmitted via a nonlinear data transmission channel comprising a first signal UL and a second signal LL. The process comprises the following: demodulating and decoding said first signal UL by means of a first demodulation and decoding chain in order to regenerate said first information UL; recoding and shaping to produce a continuous time waveform; applying a nonlinearity function based on a set of coefficients updated according to an adaptive correlation calculation process to said continuous time waveform; subtracting the result of said nonlinearity function from said composite signal in order to generate a result E; and demodulating and decoding said result E by means of a second demodulation and decoding chain in order to regenerate said second information LL.

Abstract: A method for detecting the lock-in of a loop that synchronizes an internal clock on the transmission of value pairs provided by a demodulator. According to the method, a module of a vector that has as components the values of one of the value pairs is calculated, and the module is compared with a threshold that is smaller than a theoretical module. The locked-in condition is determined according to the ratio of the number of modules found to be greater than or smaller than the threshold to the total number of modules. In one preferred method, the threshold is incremented by a first value if the module is greater than the threshold and is decremented by a second value if the module is less than the threshold. A lock-in detection circuit for detecting the lock-in of a loop is also provided. A calculation circuit calculates a module of a vector that has as components the values of one of the value pairs. A register stores a threshold and a comparator compares the stored threshold with the calculated module.

Abstract: A demodulation circuit for demodulating a received signal including carriers in quadrature modulated by digital signals and/or in which the processing is performed on two carriers in quadrature. The circuit includes a demodulator, an analog-to-digital converter, a correcting circuit, and a derotator. The correcting circuit provides signals to the derotator based on the derotator output signals and on signals provided by the analog-to-digital converter.

Abstract: The present invention relates to a demodulator provided to extract two signals modulated in phase quadrature from an intermediary frequency signal, including two analog-to-digital converters receiving the intermediary frequency signal and clocked in phase opposition by a clock at a frequency smaller than the intermediary frequency, at least equal to the bandwidth of the modulated signals, and such that the central frequency of one of the aliased spectrums of the signal converted into digital is substantially equal to half the clock frequency; and two multipliers respectively receiving the outputs of the analog-to-digital converters and receiving at the same time a sequence of values 1, −1, 1, −1, 1 . . . at the clock rate.

Abstract: A method for estimating the frequency error of a demodulator for restoring two binary signals carried on two carriers of same frequency but in phase quadrature, including the steps of forming vectors having as components the successive couples of values of the two binary signals; applying to each vector a transform which multiplies by four its angle at least when it is equal to a multiple of &pgr;/4 and which substantially preserves its module; and calculating the average of the transformed vectors. The frequency error is obtained as being the derivative of the angle of the average vector.

Abstract: The invention concerns a data transmission device comprising a turbo coder (22) comprising an interleaver operating on two interleaving blocks and means (26) for producing symbols from said codes (D, Y1, Y2) supplied by the turbo coder The device comprises means (28) for inserting a synchronising sequence into said symbols at a site having a predetermined relationship position relative to the symbols produced with the codes associated with a common interleaving block.

Abstract: The present invention relates to a digital filter for a phase-locked loop receiving at least one input signal having a predetermined period, including an element of accumulation of frequency values receiving the output of a phase detector; and an element of accumulation of phase values receiving a weighted sum of the output of the phase detector and of the content of the element of accumulation of frequency values. Each of the accumulation elements includes several frequency or phase value storage locations, circuitry being provided for successively making operative the storage locations in the phase-locked loop during a period of the input signal.

Abstract: A device for two-way digital transmission on a bus having at least one two-way line. The device includes a first pulling device for pulling a first section of the line to a first logic level, a second pulling device for pulling a second section of the line to the first logic level, and at least one two-way repeater that is connected between the first section and the second section. The repeater includes a third pulling device for pulling the first section of the line to a second logic level, a fourth pulling device for pulling the second section of the line to the second logic level, and a logic circuit that prevents the third and fourth pulling devices from being simultaneously active. In one preferred embodiment, at least one electronic circuit is connected to the first section of the line and at least one other electronic circuit is connected to the second section of the line.

Abstract: We describe the use a material which is based on microporous, filler-containing polyolefin and essentially consists of a homogeneous mixture of ultra-high molecular weight polyolefin, filler and plasticizer, for absorbing sweat and other bodily exhalations. This material is preferably treated with antibacterial and/or fungicidal agents and is suitable for avoiding the formation of odor, for example in shoes and articles of clothing. The use in the form of an inner sole which has ribs running at right angles to the longitudinal axis of the inner sole to form hollow spaces is preferred.

Abstract: The present invention relates to a method for correcting errors in a data frame including horizontal parity data enabling correction of errors in the rows of the frame based on horizontal syndromes calculated on the rows, and vertical parity data enabling correction of errors in the columns of the frame based on vertical syndromes calculated on the columns. The method includes the steps of calculating, on the fly, the horizontal and vertical syndromes of a current frame on the data of the current frame being received in a slow memory, storing these syndromes in a fast memory area, and, as the data of the next frame are being received in the slow memory, finding the values and positions of the errors of the current frame based on the syndromes stored in the fast memory area.

Abstract: Disclosed is a method and a corresponding circuit to compute the result of the division, in a Galois field of 2.sup.n =N elements, of a first number A by a second number B, these numbers being encoded on n bits, wherein said method comprises the following steps:a--the production of a first intermediate number S(1) encoded on n bits by the squaring of the first number A,b--the production of a second intermediate number R(1) encoded on n bits by the multiplication of the intermediate number S(1) by the number B,c--the performance n-2 times of the steps a and b, the intermediate numbers produced by multiplication R(j) being successively squared, and the intermediate numbers produced by squaring S(j) being successively multiplied by the second number B, andd--the production of the result S(n) by the squaring of the intermediate number R(n-1) produced by the ?n-1!th multiplication.

Abstract: A linear interpolation operator for determining the value y of a function of x when one knows the value y1 corresponding to x1, and a value y2 corresponding to x2 (where x2<x≧x1), comprises a first calculation circuit which determines the equation (xm+xM)/2; a second calculation which determines the equation (ym+yM)/2; a comparison circuit which compares x with (xm+xM)/2 so as to determine which one of the intervals [xm,(xm+xM)2], [(xm+xM)/2, xM] contains x and to feed back the limits of the selected interval into the first calculation circuit and the limits of the interval corresponding in y into the second calculation circuit.

Abstract: A device synchronizes an internal signal with respect to a reference signal, each signal comprising pulses normally occurring at a rated frequency. The device uses a phase comparator to analyze the phase of the internal signal and the reference signal and produce one logic state if the phase of the internal signal is in advance of the phase of the reference signal and a second logic state otherwise. A programmable frequency divider divides an internal clock signal by a first number if the phase comparator signal produces the first logic state or by a second number if the phase comparator produces the second logic state. A multiplexer provides the programmable divider with either the first number or the second number depending on the logic state produced the phase comparator. The device also includes a storage element for sequentially storing a predetermined number of the latest logic states of the phase comparator.

Abstract: An extractor for digital data transmitted at a first determined frequency (f0) through a video channel after a burst of 0s and 1s emitted at a first frequency (f0). A comparator (1) compares the input signal with a threshold level. A threshold level is provided by an up/down counter (12) operating at a frequency (F0) multiple of the first frequency, the up/down counting input of which is connected to the output of the comparator (1), and a digital/analog converter (16) receiving the output of the up/down counter and supplying the threshold level (V.sub.T).