Patents by Inventor Jae Chang Kwon
Jae Chang Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9123598Abstract: An array substrate of a liquid crystal display device and a method of fabricating the array substrate. A gate electrode of a thin film transistor of the array substrate is formed. The gate electrode has an edge region surrounding an interior region of the gate electrode and the edge region of the gate electrode is thicker than the interior region of the gate electrode. A semiconductor layer is formed over the gate electrode. A source electrode and a drain electrode of the thin film transistor are formed that define a channel region in the semiconductor layer. The channel region is located over the interior region of the gate electrode. Additionally, the gate electrode may be formed with a half-tone mask that results in the edge region of the gate electrode being thicker than the interior region of the gate electrode.Type: GrantFiled: March 9, 2015Date of Patent: September 1, 2015Assignee: LG Display Co., Ltd.Inventors: Jae Seok Lee, Jae Chang Kwon, Yu Ri Shim, Min Bo Kim
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Publication number: 20150179687Abstract: An array substrate of a liquid crystal display device and a method of fabricating the array substrate. A gate electrode of a thin film transistor of the array substrate is formed. The gate electrode has an edge region surrounding an interior region of the gate electrode and the edge region of the gate electrode is thicker than the interior region of the gate electrode. A semiconductor layer is formed over the gate electrode. A source electrode and a drain electrode of the thin film transistor are formed that define a channel region in the semiconductor layer. The channel region is located over the interior region of the gate electrode. Additionally, the gate electrode may be formed with a half-tone mask that results in the edge region of the gate electrode being thicker than the interior region of the gate electrode.Type: ApplicationFiled: March 9, 2015Publication date: June 25, 2015Inventors: Jae Seok LEE, Jae Chang KWON, Yu Ri SHIM, Min Bo KIM
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Patent number: 9006744Abstract: An array substrate of a liquid crystal display device and a method of fabricating the array substrate. A gate electrode of a thin film transistor of the array substrate is formed. The gate electrode has an edge region surrounding an interior region of the gate electrode and the edge region of the gate electrode is thicker than the interior region of the gate electrode. A semiconductor layer is formed over the gate electrode. A source electrode and a drain electrode of the thin film transistor are formed that define a channel region in the semiconductor layer. The channel region is located over the interior region of the gate electrode. Additionally, the gate electrode may be formed with a half-tone mask that results in the edge region of the gate electrode being thicker than the interior region of the gate electrode.Type: GrantFiled: June 26, 2013Date of Patent: April 14, 2015Assignee: LG Display Co., Ltd.Inventors: Jae Seok Lee, Jae Chang Kwon, Yu Ri Shim, Min Bo Kim
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Publication number: 20140131713Abstract: An array substrate of a liquid crystal display device and a method of fabricating the array substrate. A gate electrode of a thin film transistor of the array substrate is formed. The gate electrode has an edge region surrounding an interior region of the gate electrode and the edge region of the gate electrode is thicker than the interior region of the gate electrode. A semiconductor layer is formed over the gate electrode. A source electrode and a drain electrode of the thin film transistor are formed that define a channel region in the semiconductor layer. The channel region is located over the interior region of the gate electrode. Additionally, the gate electrode may be formed with a half-tone mask that results in the edge region of the gate electrode being thicker than the interior region of the gate electrode.Type: ApplicationFiled: June 26, 2013Publication date: May 15, 2014Inventors: Jae Seok LEE, Jae Chang KWON, Yu Ri SHIM, Min Bo KIM
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Patent number: 8610127Abstract: A thin film transistor array substrate is disclosed. The thin film transistor array substrate includes: gate lines and data lines formed to cross each other in the center of a gate insulation film on a substrate and to define pixel regions; a thin film transistor formed at each intersection of the gate and data lines; a passivation film formed on the thin film transistors; a pixel electrode formed on each of the pixel regions and connected to the thin film transistor through the passivation film; a gate pad connected to each of the gate lines through a gate linker; and a data pad connected to each of the data lines through a data linker. The data pad is formed of a gate pattern, and the data line is formed of a data pattern. The data linker is configured to connect the data pad formed of the gate pattern with the data line formed of the data pattern using a connection wiring.Type: GrantFiled: January 3, 2013Date of Patent: December 17, 2013Assignee: LG Display Co., Ltd.Inventors: Chung Wan Oh, Jae Chang Kwon, Yu Ri Shim, Chang Yeop Shin, Dong Eok Kim
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Patent number: 8368078Abstract: A thin film transistor array substrate is disclosed. The thin film transistor array substrate includes: gate lines and data lines formed to cross each other in the center of a gate insulation film on a substrate and to define pixel regions; a thin film transistor formed at each intersection of the gate and data lines; a passivation film formed on the thin film transistors; a pixel electrode formed on each of the pixel regions and connected to the thin film transistor through the passivation film; a gate pad connected to each of the gate lines through a gate linker; and a data pad connected to each of the data lines through a data linker. The data pad is formed of a gate pattern, and the data line is formed of a data pattern. The data linker is configured to connect the data pad formed of the gate pattern with the data line formed of the data pattern using a connection wiring.Type: GrantFiled: December 2, 2009Date of Patent: February 5, 2013Assignee: LG Display Co., Ltd.Inventors: Chung Wan Oh, Jae Chang Kwon, Yu Ri Shim, Chang Yeop Shin, Dong Eok Kim
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Publication number: 20100207122Abstract: A thin film transistor array substrate is disclosed. The thin film transistor array substrate includes: gate lines and data lines formed to cross each other in the center of a gate insulation film on a substrate and to define pixel regions; a thin film transistor formed at each intersection of the gate and data lines; a passivation film formed on the thin film transistors; a pixel electrode formed on each of the pixel regions and connected to the thin film transistor through the passivation film; a gate pad connected to each of the gate lines through a gate linker; and a data pad connected to each of the data lines through a data linker. The data pad is formed of a gate pattern, and the data line is formed of a data pattern. The data linker is configured to connect the data pad formed of the gate pattern with the data line formed of the data pattern using a connection wiring.Type: ApplicationFiled: December 2, 2009Publication date: August 19, 2010Inventors: Chung Wan Oh, Jae Chang Kwon, Yu Ri Shim, Chang Yeop Shin, Dong Eok Kim
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Patent number: 7768588Abstract: A thin film transistor (TFT) substrate for a liquid crystal display is provided. The thin film transistor substrate includes: a plurality of gate lines and a plurality of data lines that cross each other and define a plurality of sub-pixels; and a plurality of unit pixels in which first and second unit pixels are alternately formed in a direction of the gate lines and first and second unit pixels are formed vertically in a direction of the data lines, wherein the first unit pixel includes three sub-pixels and the first electrodes are slanted with respect to the gate lines and the data lines in each sub-pixel, the second unit pixel includes three sub-pixels and the second electrodes are a slanted with respect to the gate lines and the data lines in each sub-pixel, and the slant of the second electrodes is symmetrical to the slant of the first electrodes.Type: GrantFiled: December 22, 2006Date of Patent: August 3, 2010Assignee: LG Display Co., Ltd.Inventors: Jae Chang Kwon, Sun Yong Lee, Se Eung Lee
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Publication number: 20080002083Abstract: A thin film transistor (TFT) substrate for a liquid crystal display is provided. The thin film transistor substrate includes: a plurality of gate lines and a plurality of data lines that cross each other and define a plurality of sub-pixels; and a plurality of unit pixels in which first and second unit pixels are alternately formed in a direction of the gate lines and first and second unit pixels are formed vertically in a direction of the data lines, wherein the first unit pixel includes three sub-pixels and the first electrodes are slanted with respect to the gate lines and the data lines in each sub-pixel, the second unit pixel includes three sub-pixels and the second electrodes are a slanted with respect to the gate lines and the data lines in each sub-pixel, and the slant of the second electrodes is symmetrical to the slant of the first electrodes.Type: ApplicationFiled: December 22, 2006Publication date: January 3, 2008Inventors: Jae Chang Kwon, Sun Yong Lee, Se Eung Lee