Abstract: Proposed is a connection tube support of a waste heat recovery boiler supporting a connection tube unit having a plurality of connection tubes that is disposed inside a waste heat recovery boiler and perform heat exchange between a fluid flowing inside and exhaust gas flowing outside, wherein the connection tube support includes a header storing fluid flowing through the connection tube unit and supporting one end of the connection tube unit by being connected to one end of the connection tube unit, and a tube sheet supporting a circumferential surface of each of the plurality of connection tubes, wherein the tube sheet has the plurality of connection tubes having been passed therethrough and is provided with a plurality of support holes respectively supporting circumferential surfaces of the plurality of connection tubes having been passed therethrough.

Abstract: Disclosed herein is a once-through heat exchanger that includes a tube stack including a plurality of tubes, a plurality of heads connected to the tube stack via a connection module and configured to accommodate heated steam, the connector module comprising a plurality of tube connectors and configured to connect the tubes and the heads, and a manifold connected to the heads via a plurality of link pipes and configured to accommodate heated steam, wherein the connector module comprises a first tube connector and a second tube connector having different shapes.

Abstract: A computing system and a memory device are provided. The memory device includes a first memory having a first storage capacity. A second memory is also provided having a second storage capacity greater than the first storage capacity. The memory device also includes a controller to provide an external host with an address space corresponding to a third storage capacity, the third storage capacity being less than a sum of the first storage capacity and second storage capacity. The controller transmits the requested data to the external host from the first memory where data requested from the external host is stored in the first memory, and where the requested data is not stored in the first memory, transmits the requested data to the external host from the second memory.

Abstract: A computing system and a memory device are provided. The memory device includes a first memory having a first storage capacity, a second memory having a second storage capacity greater than the first storage capacity, and a controller to provide an external host with an address space corresponding to a third storage capacity, the third storage capacity being less than a sum of the first storage capacity and second storage capacity, wherein the controller, where data requested from the external host is stored in the first memory, transmits the requested data to the external host from the first memory, and where the requested data is not stored in the first memory, transmits the requested data to the external host from the second memory.

Abstract: A computer system includes three processors capable to operate concurrently—a scalar processor, a vector processor, and a bitstream processor. In encoding or decoding of video data, the vector processor performs operations that can be efficiently performed by a single instruction multiple data processor, for example, a discrete cosine transform (DCT) and motion compensation. The bitstream processor performs Huffman and RLC encoding or decoding. The bitstream processor can switch contexts to enable the computer system to process several data streams concurrently. The scalar and vector processors can be programmed to execute a single arithmetic or Boolean instruction. The bitstream processor cannot be programmed to execute a single arithmetic or Boolean instruction, but can be programmed to perform an entire video data processing operation. The computer system can handle different video standards. Different Huffman encoding and decoding tables are coded to share memory.

Abstract: A bidirectional discrete cosine transform (DCT) coefficient scanning apparatus includes a buffer memory, an address generator based on a look-up table for converting a first address signal to a second address signal according to a DCT coefficient scan order, a first selection section for selecting the second address signal or a third address signal as the address signal for the buffer memory, and a second selection section for selecting a quantized DCT coefficient or a decoded DCT coefficient to be written to the buffer memory during coding or decoding. During coding, quantized DCT coefficients from a quantization section are written to locations in the buffer memory identified by the third address signal, and read out to a run-length and level coding section from locations in the buffer memory identified by the second address signal.

Abstract: A multi-standard start code detector system receives an incoming compressed video bit stream. The compressed video bit stream includes start codes interspersed between variable length bit streams. Assuming error-free useful data, zero stuffing bits preceding a next start code are rapidly discarded on a bit group-wise basis. A group of current bits are processed by comparing them to a start code feature pattern. If a match is not detected, the entire group of bits is concurrently replaced by a next group. However, because the zero stuffing bits are of variable length, the exact position of the start code pattern is unknown. Preceding each replacement operation, the next group of bits is processed to predetect a start code feature. Upon predetecting a start code feature, the replacement operation is modified to ensure that a group of current data bits will include the start code feature pattern. This allows the number of searched for patterns to be reduced and streamlines the comparison operation.

Abstract: A group of incoming data stream bits having packed variable length code ("VLC") words is applied to an entropy code bit length searching module. The group of bits is replicated within a plurality of matching modules selectively distributed among entropy code bit length searching logic units. Each unit of entropy code bit length searching logic supports a VLC word table as characterized by, for example, standard compression formats such as MPEG-1, MPEG-2, H.261, and H.263. The matching modules are divided into groups within the entropy code bit length searching logic units. A group of matching modules is allocated to each VLC bit length represented in the associated VLC word supported table. A number of matching modules are allocated to each bit length equal to a minimum number of patterns unique to VLC words of a particular bit length. The matching modules compare an incoming data group to respective patterns. A detected match is indicated by an appropriately set group output signal.

Abstract: An entropy code look up table processes incoming data and provides an n-bit output signal having an entropy code word and a bit.sub.-- length output signal. Entropy code words are successively packed without spacing bits into two sixteen-bit latches. An arithmetic unit keeps track of accumulated sizes of packed, unconveyed entropy code words. The n-bit output signal is converted into a thirty-two bit signal with spacing bits on either side of a current entropy code word. Using the accumulated size information, flow through multiplexer units insert spacing bits in bit positions corresponding to bit positions currently occupied by packed entropy code words. Any remaining bits in the thirty-two bit output signal are preferably set to logical zeros. With the current entropy code word properly aligned in the thirty-two bit output signal, a path selection logic unit utilizes the accumulated size information and a unary decoder to form a sixteen bit output signal.