Abstract: A semiconductor package includes a buffer wafer including: a first surface; and a second surface opposite to the first surface, a stacked structure including a plurality of chips being stacked on the first surface of the buffer wafer; a first detection line formed around a periphery of the stacked structure on the first surface of the buffer wafer; and a mold layer covering the stacked structure, the first detection line and the first surface of the buffer wafer.

Abstract: A semiconductor package includes a buffer wafer including: a first surface; and a second surface opposite to the first surface, a stacked structure including a plurality of chips being stacked on the first surface of the buffer wafer; a first detection line formed around a periphery of the stacked structure on the first surface of the buffer wafer; and a mold layer covering the stacked structure, the first detection line and the first surface of the buffer wafer.

Abstract: Embodiments of a semiconductor package includes first semiconductor chips stacked on a substrate to form an offset stack structure, and a second semiconductor chip disposed on the substrate and electrically connected to the substrate through an input/output (I/O) wire and a ground wire. The first semiconductor chips are stacked to slope toward the second semiconductor chip. A height of the topmost portion of the ground wire from the top of the second semiconductor chip is higher than a height of the topmost portion of the I/O wire from the top of second semiconductor chip.

Abstract: A semiconductor package includes at least one semiconductor chip, an encapsulation layer encapsulating the at least one semiconductor chip, a marking layer formed on the encapsulation layer, and a product information mark formed in the marking layer.