Abstract: The semiconductor device includes: a first conductive-type first well and a second conductive-type second well configured over a substrate to contact each other; a second conductive-type anti-diffusion region configured in an interface where the first conductive-type first well contacts the second conductive-type second well over the substrate; and a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well over the substrate.

Abstract: A nonvolatile memory device includes a unit cell with a transistor and a capacitor. The transistor is disposed on a substrate having a tunneling region and a channel region and includes a floating gate crossing both the tunneling region and the channel region. The capacitor is coupled to the floating gate.

Abstract: A semiconductor device includes a second conductive-type well configured over a substrate, a first conductive-type body region configured over the second conductive-type well, a gate electrode which overlaps a portion of the first conductive-type body region, and a first conductive-type channel extension region formed over the substrate and which overlaps a portion of the gate electrode.

Abstract: The semiconductor device includes: a first conductive-type first well and a second conductive-type second well configured over a substrate to contact each other; a second conductive-type anti-diffusion region configured in an interface where the first conductive-type first well contacts the second conductive-type second well over the substrate; and a gate electrode configured to simultaneously cross the first conductive-type first well, the second conductive-type anti-diffusion region, and the second conductive-type second well over the substrate.

Abstract: A semiconductor device includes: an active region configured over a substrate to include a first conductive-type first deep well and second conductive-type second deep well forming a junction therebetween. A gate electrode extends across the junction and over a portion of first conductive-type first deep well and a portion of the second conductive-type second deep well. A second conductive-type source region is in the first conductive-type first deep well at one side of the gate electrode whereas a second conductive-type drain region is in the second conductive-type second deep well on another side of the gate electrode. A first conductive-type impurity region is in the first conductive-type first deep well surrounding the second conductive-type source region and extending toward the junction so as to partially overlap with the gate electrode and/or partially overlap with the second conductive-type source region.

Abstract: A semiconductor device includes a second conductive-type deep well configured above a substrate. The deep well includes an ion implantation region and a diffusion region. A first conductive-type first well is formed in the diffusion region. A gate electrode extends over portions of the ion implantation region and of the diffusion region, and partially overlaps the first well. The ion implantation region has a uniform impurity concentration whereas the impurity concentration of the diffusion region varies from being the highest concentration at the boundary interface between the ion implantation region and the diffusion region to being the lowest at the portion of the diffusion region that is the farthest away from the boundary interface.

Abstract: A semiconductor device includes a substrate with one or more active regions and an isolation layer formed to surround an active region and to extend deeper into the substrate than the one or more active regions. The semiconductor further includes a gate electrode, which covers a portion of the active region, and which has one end ;portion thereof extending over the isolation layer.

Abstract: Disclosed is a method of forming an isolation film in a semiconductor device. The method comprises the steps of providing a semiconductor substrate having a region where a P well will be formed and a region where a N well will be formed, forming an oxide film and a nitride film on the semiconductor substrate, removing portions of the nitride film and the oxide film and the semiconductor substrate below them to form first and second trenches in the region where the P well will be formed and the region where the N well will be formed, respectively, implementing an epitaxial growth process including a doping process to form a N type epitaxial growth layer in the first trench and a P type epitaxial growth layer in the second trench, and burying the first and second trenches with insulating films to form an isolation film.

Abstract: A method for fabricating a semiconductor device is described in which isolation layers and a collector of a BJT are simultaneously formed by an epitaxtial growth process during a process of fabricating a BiCMOS. The method for fabricating a semiconductor device of the present invention includes processes of forming a first mask layer on a semiconductor substrate, etching a predetermined portion of the semiconductor substrate with predetermined depth using the first mask layer, forming a first isolation layer on a side face of the etched semiconductor substrate, forming a first epitaxial layer doped with a plurality of layers by epitaxial growth of the exposed portion of the semiconductor substrate, forming a second mask layer on the first epitaxial layer, and forming a second epitaxial layer by epitaxial growth of a portion of the first epitaxial layer.

Abstract: The present invention discloses a method for fabricating a BiCMOS transistor, which improves the high frequency characteristics of a bipolar transistor by reducing base resistance and a parasitic capacitance between the base and collector.

Abstract: Disclosed is a method of forming a capacitor in a semiconductor device.

Abstract: A method for fabricating a complementary metal oxide semiconductor (CMOS) of a semiconductor device includes the steps of: performing an implant process to a semiconductor substrate to form N-well and P-well; patterning a gate oxide layer, a gate electrode and an etching stop layer on the semiconductor substrate formed on the semiconductor substrate sequentially; depositing a gate oxide layer and an insulating layer having a high etching ratio on the semiconductor substrate; etching the insulating layer to form a side wall spacer and to form a source/drain through an implant process; removing the gate oxide layer placed around a gate edge through a wet etching; and depositing an interlayer insulating layer on the semiconductor substrate. The method is capable of preventing a gate from deteriorating by removing a gate oxide layer at a gate edge region by processing anisotropic wet etching after a gate formation of the CMOS and a source/drain formation processes.

Abstract: Disclosed is a method of forming an isolation film in a semiconductor device. The method comprises the steps of providing a semiconductor substrate having a region where a P well will be formed and a region where a N well will be formed, forming an oxide film and a nitride film on the semiconductor substrate, removing portions of the nitride film and the oxide film and the semiconductor substrate below them to form first and second trenches in the region where the P well will be formed and the region where the N well will be formed, respectively, implementing an epitaxial growth process including a doping process to form a N type epitaxial growth layer in the first trench and a P type epitaxial growth layer in the second trench, and burying the first and second trenches with insulating films to form an isolation film.

Abstract: Disclosed is a method of forming a capacitor in a semiconductor device.

Abstract: The present invention discloses a method for fabricating a BiCMOS transistor, which improves the high frequency characteristics of a bipolar transistor by reducing base resistance and a parasitic capacitance between the base and collector.

Abstract: A method for fabricating a semiconductor device is disclosed in which isolation layers and a collector of a BJT are simultaneously formed by an epitaxtial growth process during a process of fabricating a BiCMOS. The method for fabricating a semiconductor device of the present invention includes processes of forming a first mask layer on a semiconductor substrate, etching a predetermined portion of the semiconductor substrate with predetermined depth using the first mask layer, forming a first isolation layer on a side face of the etched semiconductor substrate, forming a first epitaxial layer doped with a plurality of layers by epitaxial growth of the exposed portion of the semiconductor substrate, forming a second mask layer on the first epitaxial layer, and forming a second epitaxial layer by epitaxial growth of a portion of the first epitaxial layer.

Abstract: A method for fabricating a complementary metal oxide semiconductor (CMOS) of a semiconductor device includes the steps of: performing an implant process to a semiconductor substrate to form N-well and P-well; patterning a gate oxide layer, a gate electrode and an etching stop layer on the semiconductor substrate formed on the semiconductor substrate sequentially; depositing a gate oxide layer and an insulating layer having a high etching ratio on the semiconductor substrate; etching the insulating layer to form a side wall spacer and to form a source/drain through an implant process; removing the gate oxide layer placed around a gate edge through a wet etching; and depositing an interlayer insulating layer on the semiconductor substrate. The method is capable of preventing a gate from deteriorating by removing a gate oxide layer at a gate edge region by processing anisotropic wet etching after a gate formation of the CMOS and a source/drain formation processes.