Abstract: This application relates to a method and apparatus for outputting signals. In one aspect, the apparatus includes a signal control unit configured to generate two or more control signals upon two or more conditions, which respectively correspond to the two or more control signals being satisfied. The apparatus also includes a signal output unit configured to output a final output signal depending on the two or more control signals upon an input signal being inputted into the signal output unit.

Abstract: Provided is a method of forming an apatite coating, the method including immersing a substrate in an apatite-forming precursor solution including Ca2+ ions and PO43? ions, emitting a laser beam onto a surface of the substrate immersed in the precursor solution, and forming an apatite coating in a region exposed to the laser beam, wherein an output power of the laser beam is set within a range enabling the surface of the substrate to be melted.

Abstract: The present disclosure relates to a terminal protection device of a connector capable of protecting a terminal from an external impact, thereby preventing deformation of the terminal, and an object of the present disclosure is to provide a terminal protection device of a connector capable of implementing a terminal protection structure using a conventional moving plate with a minimum configuration.

Abstract: A semiconductor device includes first group active fins and a first diffusion prevention pattern. The first group active fins are spaced apart from each other in a second direction, and each of the first group active fins extends in a first direction different from the second direction on a first region of a substrate including the first region and a second region. The first diffusion prevention pattern extends on the first region of the substrate in the second direction through the first group active fins. The first group active fins include first and second active fins. The first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through and contacts an end of the second active fin in the first direction.

Abstract: A semiconductor device is provided. The semiconductor device includes a first cell region and a filler region that are adjacent each other in a first direction. The semiconductor device includes an active pattern extending in the first direction, inside the first cell region, a gate electrode extending in a second direction intersecting the first direction, on the active pattern, a gate contact electrically connected to an upper surface of the gate electrode, a source/drain contact electrically connected to a source/drain region of the active pattern, adjacent a side of the gate electrode, a connection wiring that extends in the first direction over the first cell region and the filler region, and is electrically connected to one of the gate contact or the source/drain contact, and a filler wiring that is inside the filler region. A related layout design method and fabricating method are also provided.

Abstract: Provided is an integrated circuit including: at least one active region extending in a first row in a first direction; at least one active region extending in a second row in the first direction; and a multiple height cell including the at least one active region in the first row, the at least one active region in the second row, at least one gate line extending in a second direction crossing the first direction, wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by a diffusion break.

Abstract: An integrated circuit includes a first standard cell including a first p-type transistor, a first n-type transistor, a first gate stack intersecting first and second active regions, first extended source/drain contacts on a first side of the first gate stack, a first normal source/drain contact on a second side of the first gate stack, a first gate via connected to the first gate stack, and a first source/drain via connected to the first normal source/drain contact, a second standard cell adjacent the first standard cell and including a second p-type transistor, a second n-type transistor, a second gate stack intersecting the first and second active regions, and a second gate via connected to the second gate stack, an input wiring connected to the first gate via, and an output wiring at a same level as the input wiring to connect the first source/drain via and the second gate via.

Abstract: A layout method is provided. The layout method may include placing first and second standard cells from a standard cell library, interconnecting the placed standard cells to generate a layout draft, confirming placement and routing at a boundary region between the interconnected standard cells, and revising the layout draft based on the confirmation. Each of the standard cells includes, in part, a conductive line that extends in the first direction and is interconnected to an adjacent standard cell through a source/drain via. To confirm the placement and routing, a first spaced distance from a tip of one of the conductive lines to a tip of the other conductive line, and a second spaced distance from the tip of the first conductive line to the cell boundary are compared with preset threshold values. Revising the layout draft may include adjusting a tip position of one of the conductive lines.

Abstract: A data storage device may include a nonvolatile memory apparatus and a controller. The controller may be configured to translate a logical address into a physical address when receiving a host command (such as a write command or a read command) including the logical address from a host device, to generate a pre-command including the physical address, to transmit the generated pre-command to the nonvolatile memory apparatus before completing one or more remaining operations of the operations used to process the host command, and to transmit a confirm command to the nonvolatile memory apparatus when the remaining operations are complete. The controller may perform the remaining operations and the transmission of the pre-command to the nonvolatile memory apparatus at the same time.

Abstract: This application relates to a method and apparatus for outputting signals. In one aspect, the apparatus includes a signal control unit configured to generate two or more control signals upon two or more conditions, which respectively correspond to the two or more control signals being satisfied. The apparatus also includes a signal output unit configured to output a final output signal depending on the two or more control signals upon an input signal being inputted into the signal output unit.

Abstract: An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

Abstract: The present disclosure relates to a terminal protection device of a connector capable of protecting a terminal from an external impact, thereby preventing deformation of the terminal, and an object of the present disclosure is to provide a terminal protection device of a connector capable of implementing a terminal protection structure using a conventional moving plate with a minimum configuration.

Abstract: A semiconductor device includes first group active fins and a first diffusion prevention pattern. The first group active fins are spaced apart from each other in a second direction, and each of the first group active fins extends in a first direction different from the second direction on a first region of a substrate including the first region and a second region. The first diffusion prevention pattern extends on the first region of the substrate in the second direction through the first group active fins. The first group active fins include first and second active fins. The first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through and contacts an end of the second active fin in the first direction.

Abstract: Provided is an integrated circuit including: at least one active region extending in a first row in a first direction; at least one active region extending in a second row in the first direction; and a multiple height cell including the at least one active region in the first row, the at least one active region in the second row, at least one gate line extending in a second direction crossing the first direction, wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by a diffusion break.

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract: A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region.

Abstract: A method of generating a photo mask for use during fabrication of a semiconductor device includes; generating an initial layout design including critical circuit paths and non-critical circuit paths by shielding all gate line patterns used to implement transistors in the critical circuits and non-critical circuits, and thereafter generating a layout design from the initial layout design by selectively un-shielding a non-critical gate line pattern among the gate line patterns used to implement a gate of a non-critical transistor in a non-critical circuit, while retaining the shielding of all critical gate line patterns among the gate line patterns.

Abstract: A new and distinct Citrus Reticulate Blanco plant named “Tamnaneunbong”, characterized by its upright plant type and strong vigor, short oval ovary shape, germination stage in middle of April, blooming stage in late May, fruits start coloring in late October, mature stage in late March, acidity of the fruit juice at about 1.51%, leaf length at about 10.1 cm and leaf width at about 4.3 cm, and length of leaf petiole at about 3.6 cm.

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract: A new and distinct Citrus reticulate Blanco plant named Tamnaneunbong, characterized by its upright plant type and strong vigor, short oval ovary shape, germination state in middle of April, blooming state in late May, fruits start coloring in late October, mature state in late March, acidity of the fruit juice at about 1.51%, leaf length at about 10.1 cm and leaf width at about 4.3 cm, and length of leaf petiole at about 3.6 cm.