Patents by Inventor Jae-Hoon Jang
Jae-Hoon Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11031411Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.Type: GrantFiled: July 8, 2019Date of Patent: June 8, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hwan Son, Jae-Hoon Jang, Jee-Hoon Han
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Publication number: 20210152079Abstract: A power conversion device comprises: a DC link capacitor charged with a DC power supplied from a power supply part; a fuse part, for breaking a current which is output from or supplied to the power supply part and has a first breaking magnitude or greater; a relay part which comprises a first relay for connecting a positive terminal of the fuse part to a positive terminal of the DC link capacitor and a second relay for connecting a negative terminal of the fuse part to a negative terminal of the DC link capacitor; an initial charge part, for charging the DC link capacitor by using DC power supplied from the power supply part; and a power conversion part for converting the direct-current power supplied from the power supply part into AC power when the DC link capacitor has been charged and supplying the alternating-current power to a load terminal.Type: ApplicationFiled: August 2, 2017Publication date: May 20, 2021Inventor: Jae-Hoon JANG
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Patent number: 11004865Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.Type: GrantFiled: November 22, 2019Date of Patent: May 11, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang Soo Kim, Shin Hwan Kang, Jae Hoon Jang, Kohji Kanamori
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Patent number: 10978464Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.Type: GrantFiled: May 14, 2020Date of Patent: April 13, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hwan Son, Jae-Hoon Jang, Jee-Hoon Han
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Patent number: 10886289Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.Type: GrantFiled: April 5, 2018Date of Patent: January 5, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Shin-hwan Kang, Young-hwan Son, Dong-seog Eun, Chang-sup Lee, Jae-hoon Jang
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Publication number: 20200381453Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.Type: ApplicationFiled: August 17, 2020Publication date: December 3, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-Yun LEE, Jae-Hoon JANG, Jae-Duk LEE, Joon-Hee LEE, Young-Jin JUNG
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Patent number: 10854630Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, a common source extension structure including a first semiconductor layer having an n-type conductivity and a gate insulating layer between the substrate and the channel structures, a plurality of gate electrodes on the common source extension structure and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension structure and including a second semiconductor layer having an n-type conductivity. An upper portion of the common source extension structure has a first width, and a lower portion of the common source extension structure has a second width smaller than the first width.Type: GrantFiled: July 30, 2019Date of Patent: December 1, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang-soo Kim, Yong-seok Kim, Tae-hun Kim, Min-kyung Bae, Jae-hoon Jang, Kohji Kanamori
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Publication number: 20200303416Abstract: A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.Type: ApplicationFiled: June 11, 2020Publication date: September 24, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Moon Kyu SONG, Ki Yoon KANG, Jae Hoon JANG
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Patent number: 10770473Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.Type: GrantFiled: September 5, 2018Date of Patent: September 8, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Yun Lee, Jae-Hoon Jang, Jae-Duk Lee, Joon-Hee Lee, Young-Jin Jung
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Publication number: 20200273870Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.Type: ApplicationFiled: May 14, 2020Publication date: August 27, 2020Inventors: Young-Hwan Son, Jae-Hoon Jang, Jee-Hoon Han
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Patent number: 10739205Abstract: Provided is a temperature sensor patch including: a base material having a lower surface that is an adhesive surface; a temperature sensor layer arranged on the base material, and including a temperature sensor at a side thereof and a connection terminal connected to the temperature sensor at the other side thereof; a cover layer configured to cover the temperature sensor layer and including a first opening exposing the connection terminal; and a module holder disposed inside the first opening, wherein a portion of the temperature sensor layer, where the connection terminal is arranged, is disposed on the module holder.Type: GrantFiled: July 17, 2017Date of Patent: August 11, 2020Assignee: HAESUNG DS CO., LTD.Inventors: Jae Hoon Jang, Ho Sang Yu, Jin Woo Lee
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Publication number: 20200234782Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.Type: ApplicationFiled: April 9, 2020Publication date: July 23, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-Il SHIM, Jae-Hoon JANG, Donghyuk CHAE, Youngho LIM, Hansoo KIM, Jaehun JEONG
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Patent number: 10685973Abstract: A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.Type: GrantFiled: April 2, 2018Date of Patent: June 16, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Moon Kyu Song, Ki Yoon Kang, Jae Hoon Jang
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Patent number: 10650903Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.Type: GrantFiled: November 30, 2018Date of Patent: May 12, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Il Shim, Jae-Hoon Jang, Donghyuk Chae, Youngho Lim, Hansoo Kim, Jaehun Jeong
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Publication number: 20200091189Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.Type: ApplicationFiled: November 22, 2019Publication date: March 19, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Kwang Soo Kim, Shin Hwan Kang, Jae Hoon Jang, Kohji Kanamori
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Patent number: 10522562Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.Type: GrantFiled: October 2, 2018Date of Patent: December 31, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Kwang Soo Kim, Shin Hwan Kang, Jae Hoon Jang, Kohji Kanamori
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Publication number: 20190355744Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.Type: ApplicationFiled: July 30, 2019Publication date: November 21, 2019Inventors: Kwang-soo KIM, Yong-seok KIM, Tae-hun KIM, Min-kyung BAE, Jae-hoon JANG, Kohji KANAMORI
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Publication number: 20190333925Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.Type: ApplicationFiled: July 8, 2019Publication date: October 31, 2019Inventors: YOUNG-HWAN SON, JAE-HOON JANG, JEE-HOON HAN
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Patent number: 10411033Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.Type: GrantFiled: May 31, 2018Date of Patent: September 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang-soo Kim, Yong-seok Kim, Tae-hun Kim, Min-kyung Bae, Jae-hoon Jang, Kohji Kanamori
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Patent number: 10396086Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.Type: GrantFiled: June 30, 2017Date of Patent: August 27, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hwan Son, Jae-Hoon Jang, Jee-Hoon Han