Abstract: The present technology relates to an electronic device. A memory device including a plurality of memory cells connected to a plurality of word lines arranged between a plurality of source select lines and a plurality of drain select lines, a peripheral circuit configured to perform a program operation of programming data in selected memory cells among the plurality of memory cells, and a program operation controller configured to control the peripheral circuit to apply a voltage, for turning on or off source select transistors connected to the plurality of source select lines, to the plurality of source select lines, while applying a pass voltage to the plurality of word lines after applying a program voltage to selected word lines connected to the selected memory cells.

Abstract: A substrate processing method is provided. The substrate processing method comprises loading a substrate onto a substrate support inside a chamber, forming a plasma inside the chamber, providing a first DC pulse signal to an electromagnet that generates a magnetic field inside the chamber and processing the substrate with the plasma, wherein the first DC pulse signal is repeated at a first period including a first section and a second section subsequent to the first section, the first DC pulse signal has a first level during the first section, and the first DC pulse signal has a second level different from the first level during the second section.

Abstract: The present disclosure relates to a method for carrying out dose delivery quality assurance for high-precision radiation treatment, in which parameters affecting a pass rate of dose delivery quality assurance can be derived through regression analysis, which is a known statistical analysis method, and a pass rate prediction model capable of predicting each parameter and the pass rate of dose delivery quality assurance can be derived, and accordingly, it can be predicted in advance whether dose delivery quality assurance will be passed according to the parameters through the above prediction model, without repeatedly carrying out dose delivery quality assurance according to a patient's treatment plan, and as a result, the efficiency of dose delivery quality assurance can be enhanced, and the time or capacity required for such quality assurance is reduced, such that radiation treatment for an actual patient can be quickly and precisely carried out.

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.

Abstract: A memory device includes a page buffer, a voltage generator, and a test controller. The page buffer is connected to a memory cell through a bit line, and is configured to sense a threshold voltage of the memory cell through a potential of a sensing node electrically connected to the bit line. The voltage generator is configured to generate a test voltage to be applied to the sensing node. The test controller is configured to control the voltage generator to apply the test voltage to the sensing node, and detect a defect of the page buffer, based on a leakage current value of the sensing node.

Abstract: A memory device includes a plurality of memory cell strings, a peripheral circuit, and control logic. The plurality of memory cell strings are connected between a bit line and a common source line. The peripheral circuit is configured to perform a channel precharge operation and a program operation for the plurality of memory cell strings. The control logic is configured to control the peripheral circuit to apply a pass voltage to a selected word line among a plurality of word lines connected to the plurality of memory cell strings and to apply a turn-on voltage to a source select line connected to the plurality of memory cell strings, during a portion of a period in which the pass voltage is applied to the selected word line, in the program operation.

Abstract: A memory device capable of reducing a peak current includes a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating the memory device includes: precharging channel regions of a plurality of memory cell strings through a common source line; and setting a bit line voltage applied to the bit line, after starting precharging the channel regions of the plurality of memory cell strings, while the channel regions of the plurality of memory cell strings are being precharged.

Abstract: A memory system includes: a nonvolatile memory device including a plurality of memory blocks each including a plurality of memory cells coupled to a plurality of word lines; and a controller configured to control the nonvolatile memory device to perform a read operation on the plurality of memory blocks, wherein the read operation includes: a first operation of supplying a first voltage level to the plurality of word lines, a second operation of discharging the plurality of word lines to a second voltage level, a third operation of supplying a third voltage level less than the first voltage level to the plurality of word lines, and a fourth operation of discharging the plurality of word lines to a fourth voltage level.

Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.

Abstract: The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.

Abstract: A memory device may include a first sub-block and a second sub-block each including a plurality of select transistors and a plurality of memory cells, a peripheral circuit performing a read operation on data stored in the first sub-block, and a control logic controlling the peripheral circuit to turn on the plurality of select transistors included in each of the first and second sub-blocks and apply a read voltage to a selected word line among a plurality of word lines.

Abstract: Provided herein is a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of sub-blocks coupled to a plurality of source select lines, respectively. The peripheral circuit performs a program operation on the memory block. The control logic is configured to control the peripheral circuit to increase a voltage of a common source line that is coupled to the memory block, increase a voltage of at least one source select line, among the plurality of source select lines, to a first voltage level, and set a voltage of a bit line that is coupled to the memory block and increase the voltage of at least one source select line from the first voltage level to a second voltage level.

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.

Abstract: A memory device and method of operating the same. A memory device includes a memory block, a peripheral circuit, and a program operation controller. The memory block includes a first sub block connected to a first drain select line and a first source select line, and a second sub block connected to a second drain select line and a second source select line, and each of the first sub block and the second sub block is connected to a plurality of word lines and a common source line. The program operation controller controls the peripheral circuit to transfer a precharge voltage to the channel region through the common source line or a plurality of bit lines connected the memory block, and to apply a control voltage to the first and second source select lines at different time points or to apply the control voltage to the first and second drain select lines at different time points in the step of precharging the channel region.

Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells and a plurality of select transistors; a peripheral circuit for performing a program operation on selected select transistors among the plurality of select transistors in a select transistor program operation; and a control logic for controlling the peripheral circuit to perform the select transistor program operation. The peripheral circuit applies a coupling voltage having a positive potential to a source line of the memory block in the select transistor program operation.

Abstract: A memory device includes a page buffer, a voltage generator, and a test controller. The page buffer is connected to a memory cell through a bit line, and is configured to sense a threshold voltage of the memory cell through a potential of a sensing node electrically connected to the bit line. The voltage generator is configured to generate a test voltage to be applied to the sensing node. The test controller is configured to control the voltage generator to apply the test voltage to the sensing node, and detect a defect of the page buffer, based on a leakage current value of the sensing node.

Abstract: The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.

Abstract: A memory device capable of reducing a peak current includes a plurality of memory cell strings each including a plurality of memory cells connected between a common source line and a bit line, a source select line connected between the common source line and the plurality of memory cells, and a drain select line connected between the bit line and the plurality of memory cells. A method for operating the memory device includes: precharging channel regions of a plurality of memory cell strings through a common source line; and setting a bit line voltage applied to the bit line, after starting precharging the channel regions of the plurality of memory cell strings, while the channel regions of the plurality of memory cell strings are being precharged.

Abstract: A memory device includes a plurality of memory cell strings, a peripheral circuit, and control logic, The plurality of memory cell strings are connected between a bit line and a common source line. The peripheral circuit is configured to perform a channel precharge operation and a program operation for the plurality of memory cell strings. The control logic is configured to control the peripheral circuit to apply a pass voltage to a selected word line among a plurality of word lines connected to the plurality of memory cell strings and to apply a turn-on voltage to a source select line connected to the plurality of memory cell strings, during a portion of a period in which the pass voltage is applied to the selected word line, in the program operation.

Abstract: Provided herein is a semiconductor memory device and a method of operating the same, The semiconductor memory device includes a memory block, a peripheral circuit, and a control logic. The memory block includes a plurality of sub-blocks coupled to a plurality of source select lines, respectively. The peripheral circuit performs a program operation on the memory block. The control logic is configured to control the peripheral circuit to increase a voltage of a common source line that is coupled to the memory block, increase a voltage of at least one source select line, among the plurality of source select lines, to a first voltage level, and set a voltage of a bit line that is coupled to the memory block and increase the voltage of at least one source select line from the first voltage level to a second voltage level.