Abstract: An integrated circuit includes a data processing circuit, an electrostatic discharge (ESD) protection circuit which is connected between a voltage rail and a ground rail and protects the data processing circuit from an ESD event on the voltage rail, and a switch circuit for controlling a connection between the voltage rail and the data processing circuit in response to a control signal.

Abstract: An electrostatic discharge (ESD) protection device includes an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor including a source electrode, a gate electrode, and a well bias electrode that are connected to a first pad receiving a first voltage, and a drain electrode connected to a middle node. The ESD protection device further includes a silicon controlled rectifier (SCR) connected between the middle node and a second pad receiving a second voltage higher than the first voltage.

Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

Abstract: An integrated circuit includes a data processing circuit, an electrostatic discharge (ESD) protection circuit which is connected between a voltage rail and a ground rail and protects the data processing circuit from an ESD event on the voltage rail, and a switch circuit for controlling a connection between the voltage rail and the data processing circuit in response to a control signal.

Abstract: An electrostatic discharge (ESD) protection device includes an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor including a source electrode, a gate electrode, and a well bias electrode that are connected to a first pad receiving a first voltage, and a drain electrode connected to a middle node. The ESD protection device further includes a silicon controlled rectifier (SCR) connected between the middle node and a second pad receiving a second voltage higher than the first voltage.

Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

Abstract: A semiconductor apparatus that includes: a first high-voltage transistor having a gate and a first electrode, wherein the first electrode is connected to a first pad and a parasitic capacitance forms between the gate and the first electrode; and a clamping circuit that is connected to the gate of the first high-voltage transistor, wherein the clamping circuit detects a change in a level of a gate voltage of the first high-voltage transistor due to electrostatic discharge, and clamps the gate voltage of the first high-voltage transistor according to a result of the detection.

Abstract: A method of manufacturing a diode is provided. An N-type well region is formed in a first upper portion of an N-type epitaxial layer. A P-type drift region is formed in a second upper portion of the N-type epitaxial layer. An N-type doping region is formed in the N-type well region. A P-type doping region is formed in the P-type drift region. An isolation structure is formed in the P-type drift region. The isolation structure is disposed between the P-type doping region and the N-type well region. A first electrode is formed on a portion of the N-type epitaxial layer. The portion of the N-type epitaxial layer is disposed between the N-type well region and the P-type drift region. The first electrode overlaps a portion of the isolation structure. A connection structure is formed to electrically couple the N-type doping region and the first electrode.

Abstract: A method of manufacturing a diode is provided. An N-type well region is formed in a first upper portion of an N-type epitaxial layer. A P-type drift region is formed in a second upper portion of the N-type epitaxial layer. An N-type doping region is formed in the N-type well region. A P-type doping region is formed in the P-type drift region. An isolation structure is formed in the P-type drift region. The isolation structure is disposed between the P-type doping region and the N-type well region. A first electrode is formed on a portion of the N-type epitaxial layer. The portion of the N-type epitaxial layer is disposed between the N-type well region and the P-type drift region. The first electrode overlaps a portion of the isolation structure. A connection structure is formed to electrically couple the N-type doping region and the first electrode.

Abstract: A semiconductor apparatus that includes: a first high-voltage transistor having a gate and a first electrode, wherein the first electrode is connected to a first pad and a parasitic capacitance forms between the gate and the first electrode; and a clamping circuit that is connected to the gate of the first high-voltage transistor, wherein the clamping circuit detects a change in a level of a gate voltage of the first high-voltage transistor due to electrostatic discharge, and clamps the gate voltage of the first high-voltage transistor according to a result of the detection.

Abstract: A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.

Abstract: An electrostatic discharge (ESD) protection element includes a first diode, a second diode, and a poly resistor. The first diode is connected between a first voltage and an input/output (I/O) pad. The second diode is connected between the I/O pad and a second voltage. The poly resistor is formed on the second diode.

Abstract: A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, at least two first well regions which have a second conductivity type and a predetermined depth in the semiconductor substrate, at least one second well region which has the first conductivity type and a predetermined depth in each of the first well regions, and a guard-ring region which has the second conductivity type and a predetermined depth and is positioned between the first well regions to be separated by a predetermined distance from the first well regions. The guard-ring region is connected to a ground voltage.

Abstract: A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads.

Abstract: An electrostatic discharge (ESD) protection element includes a first diode, a second diode, and a poly resistor. The first diode is connected between a first voltage and an input/output (I/O) pad. The second diode is connected between the I/O pad and a second voltage. The poly resistor is formed on the second diode.

Abstract: There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a VDD ESD protection element connected between an I/O pad and a VDD line, a ground voltage (VSS) ESD protection element connected between the I/O pad and a VSS line, and a power clamp element connected between the VDD line and the VSS line, and wherein the VDD ESD protection element, the power clamp element, and the VSS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.

Abstract: A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.