Patents by Inventor Jae-hyoung Choi

Jae-hyoung Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11945744
    Abstract: Disclosed are a method and apparatus for reusing wastewater. The method for reusing wastewater disclosed herein includes: generating a mixed wastewater by mixing multiple types of wastewater (S20); performing a first purification by passing the mixed wastewater through a flocculation-sedimentation unit (S40); performing a second purification by passing an effluent of the flocculation-sedimentation unit through a membrane bioreactor (MBR) (S60); performing a third purification by passing an effluent of the MBR through a reverse-osmosis membrane unit (S80); and reusing an effluent of the reverse-osmosis membrane unit as cooling water or industrial water (S100).
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: April 2, 2024
    Assignees: SAMSUNG ENGINEERING CO., LTD., SAMSUNG ELECTRONICS CO., LTD
    Inventors: Seok Hwan Hong, Dae Soo Park, Seung Joon Chung, Yong Xun Jin, Jae Hyung Park, Jae Hoon Choi, Jae Dong Hwang, Jong Keun Yi, Su Hyoung Cho, Kyu Won Hwang, June Yurl Hur, Je Hun Kim, Ji Won Chun
  • Publication number: 20240014252
    Abstract: A semiconductor device includes a substrate, first and second supporter patterns spaced vertically from the substrate, the second supporter pattern being spaced vertically from the first supporter pattern, a lower electrode hole extending vertically on the substrate, a lower electrode inside the lower electrode hole, contacting a sidewall of the first and second supporter patterns, the lower electrode including a first layer along a portion of a sidewall and bottom surface of the lower electrode hole, a second layer between the first layers, and a third layer on an upper surface of the first and second layers, the first and second layers including a material different from the second layer, and a sidewall of at least a portion of the third layer being concave toward the third layer, overlapping the second layer in the vertical direction, and being spaced apart from the second layer in the vertical direction.
    Type: Application
    Filed: March 10, 2023
    Publication date: January 11, 2024
    Inventors: Hong Sik CHAE, Tae Kyun KIM, Ji Hoon AN, Hyun-Suk LEE, Gi Hee CHO, Jae Hyoung CHOI
  • Publication number: 20230061185
    Abstract: A semiconductor device is provided. The semiconductor device comprises a lower electrode, a lower dielectric layer on the lower electrode, an upper electrode on the lower dielectric layer, an upper dielectric layer formed between the lower dielectric layer and the upper electrode, and an interposed electrode film formed between the lower dielectric layer and the upper dielectric layer, wherein the upper dielectric layer includes titanium oxide.
    Type: Application
    Filed: March 30, 2022
    Publication date: March 2, 2023
    Inventors: Intak JEON, Han Jin LIM, Hyung Suk JUNG, Jae Hyoung CHOI
  • Patent number: 11177263
    Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: November 16, 2021
    Inventors: Se-hyoung Ahn, Youn-soo Kim, Jae-hyoung Choi, Jae-wan Chang, Sun-min Moon, Jin-sun Lee
  • Patent number: 10829881
    Abstract: The present disclosure provides a door lock device for releasably locking a door of a washing machine. The door lock device has first to third latches, and a drive motor and a latch drive mechanism for moving the third latch. The first latch releasably locks the door of the washing machine and is movable in frontward and rearward directions. The movement of the first latch is changed at a change position. The first latch is always biased frontward by a spring. The second latch releasably locks the first latch, which locks the door of the washing machine, at a door locking position. The third latch is moved in a direction perpendicular to the movement direction of the first latch. The third latch restricts the first latch at the door locking position, or unlocks the first latch after pushing the first latch from the door locking position against the spring.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: November 10, 2020
    Assignee: SCD CO., LTD.
    Inventor: Jae Hyoung Choi
  • Publication number: 20200243531
    Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.
    Type: Application
    Filed: March 23, 2020
    Publication date: July 30, 2020
    Inventors: Se-hyoung Ahn, Youn-soo Kim, Jae-hyoung Choi, Jae-wan Chang, Sun-min Moon, Jin-sun Lee
  • Patent number: 10636795
    Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: April 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-hyoung Ahn, Youn-soo Kim, Jae-hyoung Choi, Jae-wan Chang, Sun-min Moon, Jin-sun Lee
  • Publication number: 20190267384
    Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.
    Type: Application
    Filed: May 15, 2019
    Publication date: August 29, 2019
    Inventors: Se-hyoung Ahn, Youn-soo Kim, Jae-hyoung Choi, Jae-wan Chang, Sun-min Moon, Jin-sun Lee
  • Patent number: 10297600
    Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-hyoung Ahn, Youn-soo Kim, Jae-hyoung Choi, Jae-wan Chang, Sun-min Moon, Jin-sun Lee
  • Publication number: 20180240800
    Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.
    Type: Application
    Filed: April 18, 2018
    Publication date: August 23, 2018
    Inventors: Se-hyoung Ahn, Youn-soo Kim, Jae-hyoung Choi, Jae-wan Chang, Sun-min Moon, Jin-sun Lee
  • Patent number: 9978753
    Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-hyoung Ahn, Youn-soo Kim, Jae-hyoung Choi, Jae-wan Chang, Sun-min Moon, Jin-sun Lee
  • Patent number: 9923047
    Abstract: The inventive concepts provide semiconductor devices and methods for manufacturing the same in which the method includes forming a capacitor including a bottom electrode, a dielectric layer and a top electrode sequentially stacked on a substrate, and also where formation of the top electrode includes forming a first metal nitride layer on the dielectric layer, and forming a second metal nitride layer on the first metal nitride layer, in which the first metal nitride layer is disposed between the dielectric layer and the second metal nitride layer, and the first metal nitride layer is formed at a temperature lower than a temperature at which the second metal nitride layer is formed.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se Hoon Oh, Seongyul Park, Chin Moo Cho, Yunjung Choi, Gyu-Hee Park, Youn-Joung Cho, Younsoo Kim, Jae Hyoung Choi
  • Patent number: 9893142
    Abstract: A method of manufacturing a semiconductor device includes forming a lower metal layer, forming an interfacial oxide film on the lower metal layer, providing a metal precursor on the interfacial oxide film at a first pressure to adsorb the metal precursor into the interfacial oxide film, performing a first purge process at a second pressure to remove the unadsorbed metal precursor, the second pressure lower than the first pressure, providing an oxidizing gas at the first pressure to react with the adsorbed metal precursor, performing a second purge process at the second pressure to remove the unreacted oxidizing gas and form a dielectric film, and forming an upper metal layer on the dielectric film.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: February 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Hyoung Ahn, Young-Geun Park, Jong-Bom Seo, Jae-Hyoung Choi
  • Publication number: 20170352666
    Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.
    Type: Application
    Filed: January 19, 2017
    Publication date: December 7, 2017
    Inventors: Se-hyoung Ahn, Youn-soo Kim, Jae-hyoung Choi, Jae-wan Chang, Sun-min Moon, Jin-sun Lee
  • Patent number: 9685498
    Abstract: To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: June 20, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yeol Kang, Suk-Jin Chung, Youn-Soo Kim, Jae-Hyoung Choi, Jae-Soon Lim, Min-Young Park
  • Patent number: 9685450
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: June 20, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Yeon Park, Jae-Hyoung Choi, Vladimir Urazaev, Jin-Ha Jeong
  • Publication number: 20170145613
    Abstract: The present disclosure provides a door lock device for releasably locking a door of a washing machine. The door lock device has first to third latches, and a drive motor and a latch drive mechanism for moving the third latch. The first latch releasably locks the door of the washing machine and is movable in frontward and rearward directions. The movement of the first latch is changed at a change position. The first latch is always biased frontward by a spring. The second latch releasably locks the first latch, which locks the door of the washing machine, at a door locking position. The third latch is moved in a direction perpendicular to the movement direction of the first latch. The third latch restricts the first latch at the door locking position, or unlocks the first latch after pushing the first latch from the door locking position against the spring.
    Type: Application
    Filed: November 21, 2016
    Publication date: May 25, 2017
    Applicant: SCD CO., LTD.
    Inventor: Jae Hyoung CHOI
  • Publication number: 20170018604
    Abstract: A method of manufacturing a semiconductor device includes forming a lower metal layer, forming an interfacial oxide film on the lower metal layer, providing a metal precursor on the interfacial oxide film at a first pressure to adsorb the metal precursor into the interfacial oxide film, performing a first purge process at a second pressure to remove the unadsorbed metal precursor, the second pressure lower than the first pressure, providing an oxidizing gas at the first pressure to react with the adsorbed metal precursor, performing a second purge process at the second pressure to remove the unreacted oxidizing gas and form a dielectric film, and forming an upper metal layer on the dielectric film.
    Type: Application
    Filed: March 29, 2016
    Publication date: January 19, 2017
    Inventors: Se-Hyoung AHN, Young-Geun PARK, Jong-Bom SEO, Jae-Hyoung CHOI
  • Publication number: 20160315137
    Abstract: To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.
    Type: Application
    Filed: July 5, 2016
    Publication date: October 27, 2016
    Inventors: SANG-YEOL KANG, SUK-JIN CHUNG, YOUN-SOO KIM, JAE-HYOUNG CHOI, JAE-SOON LIM, MIN-YOUNG PARK
  • Patent number: 9412583
    Abstract: To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: August 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yeol Kang, Suk-Jin Chung, Youn-Soo Kim, Jae-Hyoung Choi, Jae-Soon Lim, Min-Young Park