Abstract: A driving circuit of a data electrode is provided which includes a drive controlling unit, a first driving transistor and a second driving transistor. The drive controlling unit compares a previous data signal and a present data signal in response to an energy recovery enable signal and outputs a first driving signal and a second driving signal, which correspond to the comparison result. The first driving transistor transmits an address driving signal to an output node connected to the data electrode in response to the first driving signal. The second driving transistor transmits a reference voltage to the output node in response to the second driving signal.

Abstract: A driving circuit of a data electrode is provided which includes a drive controlling unit, a first driving transistor and a second driving transistor. The drive controlling unit compares a previous data signal and a present data signal in response to an energy recovery enable signal and outputs a first driving signal and a second driving signal, which correspond to the comparison result. The first driving transistor transmits an address driving signal to an output node connected to the data electrode in response to the first driving signal. The second driving transistor transmits a reference voltage to the output node in response to the second driving signal.

Abstract: A method for driving M address electrodes included in a plasma display panel in an address period for selecting specific discharge cells from discharge cells of N rows and M columns that applies a driving voltage rising in two stages from a reference voltage to an address voltage to the M address electrodes in a period of the address period that corresponds to a first row and applies a driving voltage tailing in two stages from the address voltage to the reference voltage to the M address electrodes in a period of the address period that corresponds to an Nth row when the discharge cells of N rows and M columns are all selected.

Abstract: Provided are a bi-directional high voltage switching device that includes an N-channel double diffused metal oxide semiconductor field effect transistor (DMOS FET) and a P-channel DMOS FET, each conducting current bi-directionally, and an energy recovery circuit that reduces the amount of energy consumed when charging or discharging a load capacitor by efficiently driving the bi-directional high voltage switching device; where the N-channel symmetric DMOS FET and the P-channel symmetric DMOS FET are connected to each other in parallel; and the energy recovery circuit includes a pull-up device, a pull-down device, an energy recovery capacitor, and a bi-directional high voltage switching device.

Abstract: A pull-up transistor array for a high voltage output circuit is provided. The transistor array includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate and N double diffused MOS transistors (DMOS transistors) laterally arranged on the epitaxial layer. One of source/drains of the DMOS transistors is formed at each of transistors, and the N DMOS transistors share another source/drain. Accordingly, the pull-up transistor array may output a signal of a high voltage and high current, and may high-integrate a device because a device isolation region is not required between the DMOS transistors.

Abstract: Provided are a bi-directional high voltage switching device that includes an N-channel double diffused metal oxide semiconductor field effect transistor (DMOS FET) and a P-channel DMOS FET, each conducting current bi-directionally, and an energy recovery circuit that reduces the amount of energy consumed when charging or discharging a load capacitor by efficiently driving the bi-directional high voltage switching device; where the N-channel symmetric DMOS FET and the P-channel symmetric DMOS FET are connected to each other in parallel; and the energy recovery circuit includes a pull-up device, a pull-down device, an energy recovery capacitor, and a bi-directional high voltage switching device.

Abstract: A pull-up transistor array for a high voltage output circuit is provided. The transistor array includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate and N double diffused MOS transistors (DMOS transistors) laterally arranged on the epitaxial layer. One of source/drains of the DMOS transistors is formed at each of transistors, and the N DMOS transistors share another source/drain. Accordingly, the pull-up transistor array may output a signal of a high voltage and high current, and may high-integrate a device because a device isolation region is not required between the DMOS transistors.