Abstract: An aging monitoring circuit of a semiconductor memory device includes a threshold voltage sensing part including an aging monitoring transistor, enabled in response to activation of an aging monitoring signal, and generating a sensing threshold signal, a level of the sensing threshold signal depending on a threshold voltage of the aging monitoring transistor, a reference threshold storage part receiving the sensing threshold signal generated in response to activation of a reference sensing signal and storing a reference threshold voltage, a level of the reference threshold voltage depending on the level of the sensing threshold signal, and a level comparing part enabled in response to the activation of the aging monitoring signal and generating an aging flag signal, a logic state of the aging flag signal depending on a comparison result between the level of the sensing threshold signal and the level of the reference threshold voltage.

Abstract: In the semiconductor memory device of the disclosure, a half of the 1-st dummy memory cells of the 1-st dummy memory array and a half of the 2-nd dummy cells of the 2-nd dummy memory array can store data. In the semiconductor memory device of the disclosure, dummy memory cells corresponding to one normal memory array may be used to store data. As a result, according to the semiconductor memory device of the disclosure, the degree of integration may be greatly improved.

Abstract: Provided is a spike neural network circuit including a synapse configured to generate an operation signal based on an input spike signal and a weight, and a neuron configured to generate an output spike signal using a comparator configured to compare a voltage of a membrane signal generated based on the operation signal with a voltage of a threshold signal, wherein the comparator includes a bias circuit configured to conditionally supply a bias current of the comparator depending on the membrane signal.

Abstract: Disclosed is a spike neural network circuit including a synaptic circuit including synapses arranged in rows and columns, an axon circuit that generates a first input spike signal to be provided to a first row among the rows, and a second input spike signal to be provided to a second row among the rows, an input spike detecting circuit that generates an enable signal when detecting a pulse from at least one of the first input spike signal and the second input spike signal, and a first neuron circuit that compares a voltage level of a first accumulated signal, which is output from a first column among the columns, with a threshold voltage level in response to the enable signal, and outputs a first output spike signal when the voltage level of the first accumulated signal exceeds the threshold voltage level.

Abstract: Disclosed is a spike neural network circuit including a weight storage that receives an input spike signal and outputs data based on a weight, a charge sharing synaptic circuit that generates a synaptic voltage based on the output data, a switched capacitor circuit that naturally discharges the generated synaptic voltage, a voltage-to-current conversion circuit that receives the synaptic voltage and generates a membrane voltage, and a neuron circuit that receives the membrane voltage and a threshold voltage and generates an output spike signal based on the received membrane voltage and the received threshold voltage.

Abstract: Disclosed is a spike neural network circuit which includes a pulse generator that receives an input spike signal and generates a first modulation pulse and a second modulation pulse based on the input spike signal, first and second current source arrays controlled based on a weight memory, a membrane capacitor, a first switch that delivers a first calculation signal generated from the first current source array to the membrane capacitor, in response to the first modulation pulse, and a second switch that delivers a second calculation signal generated from the second current source array to the membrane capacitor, in response to the second modulation pulse.

Abstract: A signal input buffer includes 1-st and 2-nd buffering blocks; a 1-st input switching block; a 2-nd input switching block; a 1-st output switching block; and a 2-nd output switching block. The signal input buffer buffers a reception signal pair and generates a buffered signal pair, and is capable of operation in a normal mode and a calibration mode, the reception signal pair includes an intrinsic reception signal and a complementary reception signal, the buffered signal pair includes an intrinsic buffered signal and a complementary buffered signal, and the calibration mode includes a 1-st calibration period and a 2-nd calibration period.

Abstract: Disclosed is a method of operating a system-on-chip automatic design device. The system-on-chip automatic design device includes a first synthesizer and a second synthesizer. The method includes generating a first code, based on information of a first signal and information of a second signal that are used in a first IP (Intellectual Property) block, classifying a first signal code corresponding to the first signal and a second signal code corresponding to the second signal from the first code, synthesizing, through the first synthesizer, a first communication architecture configured to transmit the first signal, based on the classified first signal code, and synthesizing, through the second synthesizer, a second communication architecture configured to transmit the second signal based on the classified second signal code.

Abstract: A data input buffer includes a switching circuit; a reception circuit that includes a reception response unit and a reference response unit; and a code generating circuit. The data input buffer buffers a reception data signal to generate a buffered data signal, the reception data signal being an analog signal, and the buffered data signal being a digital signal, and a relative magnitude of a reference response conductance with respect to the reception response conductance is sequentially changed according to a sequential change of the calibration code, in the calibration mode.

Abstract: Disclosed is a neuron circuit, which includes a first bias circuit that adds a bias current to an input current to generate a biased input current, a logarithm-based neuron calculation circuit that performs a logarithm calculation on an amount of current of the biased input current to generate an input logarithm value and generates a biased output voltage by performing a logarithm-based Hodgkin-Huxley model calculation based on the input logarithm value, and a second bias circuit that adds a bias voltage to the biased output voltage to generate an output voltage.

Abstract: A neuron circuit including a first internal circuit that receives a plurality of spike input signals, generates a first sum value by summing a plurality of synaptic weights corresponding to the plurality of spike input signals, and outputs a second sum value by adding a membrane potential value to the first sum value, a spike generating circuit that generates a spike output signal, a membrane potential generating circuit that generates the membrane potential value, a second internal circuit that counts a last spike time based on the spike output signal, and an online learning circuit that receives a last input time from the first internal circuit and performs LTP learning based on the last input time or receives the last spike time from the second internal circuit and performs LTD learning based on the last spike time.

Abstract: An analog-to-digital converter may comprise a code voltage generating part that generates a conversion code voltage according to the conversion digital code; a voltage comparing part that generates a comparison result signal by comparing the input analog voltage and the conversion code voltage; a shifting register that receives a clock signal and generates a 1-st to a n-th control pulse signals; and a code generating part that generates the conversion digital code with receiving by comparison result signal and the 1-st to the n-th control pulse signals.

Abstract: Disclosed herein is a semiconductor memory device for reducing data read time difference between memory banks. In the semiconductor memory device of the disclosure, each of the memory banks has the delay control time controlled based on the distance from data control block or receives the signal according to the read command. Accordingly, the data read time difference is reduced in the semiconductor memory device, and the operation time margin of the data control block is improved.

Abstract: An auto refresh limiting circuit includes an oscillating signal generating part that generates an internal oscillating signal, the internal oscillating signal being a pulse having a period reflecting an internal temperature of a semiconductor memory device; a masking signal generating part that generates a masking signal by using an auto refresh command signal and the internal oscillating signal, the masking signal being deactivated during a pulse of the auto refresh command signal, the pulse of the auto refresh command signal being first generated after the pulse of the internal oscillating signal is generated; and an auto refresh masking part that converts the pulse of the auto refresh command signal into a pulse of an auto refresh driving signal, the conversion of the pulse of the auto refresh driving signal being masked according to the activation of the masking signal.

Abstract: Disclosed is a spike neural network circuit including an axon circuit that generates a first input spike signal, a conversion table that converts a first fire probability of a first neuron corresponding to the first input spike signal into a first threshold value, and a probabilistic operator. The probabilistic operator includes a random number generator that generates a random number value based on an event that the first input spike signal is at a first logic level, a random number comparator that generates a first comparison signal by comparing the first threshold value with the random number value, and a spike generator that generates an output spike signal corresponding to the first neuron based on an event that the first comparison signal is at the first logic level.

Abstract: An input buffer circuit includes a reception sensing part that receives an input signal pair to generate an intermediate signal pair, a comparison buffering part that buffers the intermediate signal pair to generate a buffered signal pair, an intrinsic buffered signal of the buffered signal pair being controlled to a first logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, a complementary buffered signal of the buffered signal pair is controlled to a second logic state as a level of the intrinsic intermediate signal is higher than a level of the complementary intermediate signal, and a hysteresis control part that drives the buffered signal pair to have forward hysteresis by using at least one of the intrinsic buffered signal and the complementary buffered signal.

Abstract: Provided is a capsule endoscope. The capsule endoscope includes: an imaging device configured to perform imaging on a digestive tract in vivo to generate an image; an artificial neural network configured to determine whether there is a lesion area in the image; and a transmitter configured to transmit the image based on a determination result of the artificial neural network.

Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

Abstract: A gas-detecting apparatus includes a pump module connected to a first input and a second input to intake air, a sensor module including at least one unit sensor configured to output a sensing signal in response to gas present in the air, and a control module configured to detect the gas using the sensing signal. The control module controls the pump module to intake second air by opening the second input when gas is detected in first air introduced through the first input, and determines that gas is detected when a concentration of gas detected in the second air is lower than a concentration of gas detected in the first air.

Abstract: Disclosed are a biometric authentication device and a fingerprint authentication device including the same. The biometric authentication device includes a clock generator that generates a clock signal, an authentication signal generator that generates an authentication signal based on the clock signal, a transmission electrode that transmits the authentication signal to a contact body, a reception electrode that receives a channel pass signal in which the authentication signal passes through a channel of the contact body, and a biometric authenticator that restores the channel pass signal and compares the restored channel pass signal with the authentication signal to generate a biometric authentication signal indicating whether the contact body is a biological tissue. According to the present disclosure, it is possible to improve the security of a fingerprint authentication device.