Abstract: A frame module includes a frame configured to enclose a portion of a user, and at least one reinforcement belt of which both end portions are connected to both sides of the frame, thereby restricting a splaying level of the frame in a predetermined direction.

Abstract: Provided are a method for generating a summary and a system therefor. The method according to some embodiments may include calculating a likelihood loss for a summary model using a first text sample and a first summary sentence corresponding to the first text sample, calculating an unlikelihood loss for the summary model using a second text sample and the first summary sentence, the second text sample being a negative sample generated from the first text sample, and updating the summary model based on the likelihood loss and the unlikelihood loss.

Abstract: A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.

Abstract: The invention relates to a side-emission type LED package capable of minimizing light loss to achieve high luminance and to a backlight unit using the same. The LED package includes a lead frame with an electrode formed thereon and a light emitting diode chip disposed on the lead frame. The LED package further includes a body made of molded material surrounding the light emitting diode chip disposed on the lead frame, the body having an asymmetrical shape; and a reflecting part extended from a side of the body to downwardly reflect light emitted from the light emitting diode chip. The reflecting part is extended from the upper edge of the body housing the LED chip to effectively block light from leaking outside, thereby achieving high-luminance emission.

Abstract: A side view LED package for a backlight unit includes a package body having a cavity with an inclined inner sidewall, first and second lead frames arranged in the package body, the cavity of the package body exposing a portion of at least one of the first and second lead frames placed in a bottom of the cavity to outside, a light emitting diode chip mounted on the bottom of the cavity to be electrically connected to the first and second lead frames, and a transparent encapsulant arranged in the cavity surrounding the light emitting diode chip. The cavity has a depth larger than a mounting height of the light emitting diode chip and not exceeding six times of the mounting height. The height of the sidewall is shortened to improve beam angle characteristics of emission light, increase light quantity, and prevent a molding defect of the sidewall.

Abstract: A side view LED includes an insulating substrate, and first and second metal layers each having first and second areas spaced apart from each other at a predetermined gap and disposed on top and underside surfaces of the insulating substrate, respectively. First and second electrical connectors are formed in a thickness direction of the insulating substrate, connecting the first area of the first metal layer to that of the second metal layer, and the second area of the first metal layer to that of the second metal layer. An LED chip is mounted on the first metal layer and electrically connected to the first and second areas. Also, a wall part is attached to the first metal layer to form an opened area around the LED chip. A protective device is mounted on an underside surface of the second metal layer and electrically connected to the first and second areas.

Abstract: The present invention relates to a light source-guide structure having an LED as a light source and a backlight apparatus having the same. The light source-guide structure includes a light guide plate with grooves formed in a peripheral side thereof and a light source having a transparent package fitted into the groove of the light guide plate with an LED chip inside the transparent package. The structure also includes a wiring substrate for seating the LED chip and reflecting the light from the LED chip to the light guide plate and a reflection layer attached on upper surfaces of the light source and the light guide plate. With the light source inserted into the light guide plate, the loss of light is minimized while the horizontal beam angle of light from the LED is increased, minimizing the peripheral area.

Abstract: A CMOS image capture device includes an array of pixel elements configured to convert an image received as light at a surface thereof into analog output signals. An image processing circuit is also provided. The image processing circuit is configured to generate digital output signals from which the image can be recreated in response to the analog output signals. The image processing circuit has self-adjustable gain characteristics. The image processing circuit includes a ramp signal generator having an integration circuit therein with an adjustable RC time constant. The integration circuit includes an operational amplifier and a resistor array and/or a capacitor array electrically coupled to the operational amplifier. This resistor array and/or capacitor array enables the adjustable RC time constant.

Abstract: Disclosed is a method for forming a capacitor of a semiconductor device. In such a method, a mold insulating layer is formed on an insulating interlayer provided with a storage node plug, and the mold insulating layer is etched to form a hole through which the storage node plug is exposed. Next, a metal storage electrode with an interposed WN layer is formed on a hole surface including the exposed storage node plug and the mold insulating layer is removed. Finally, a dielectric layer and a plate electrode are formed in order on the metal storage electrode.

Abstract: A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.