Patents by Inventor Jae Seok KANG

Jae Seok KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240186070
    Abstract: A multilayer electronic component has a body and a non-conductive resin layer. The non-conductive resin layer includes a body cover portion disposed in a region of an external surface of the body in which an electrode layer of an external electrode is not disposed, and an extending portion extending from the body cover portion between the electrode layer and a conductive resin layer of the external electrode, to thereby suppress arc discharge, improve bending strength, and improve moisture resistance.
    Type: Application
    Filed: February 13, 2024
    Publication date: June 6, 2024
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Seok YI, Jung Min KIM, Bon Seok KOO, Chang Hak CHOI, Il Ro LEE, Byung Woo KANG, San KYEONG, Hae Sol KANG
  • Patent number: 11963467
    Abstract: An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: April 16, 2024
    Assignee: SK hynix Inc.
    Inventors: Hyo-June Kim, Hyun-Seok Kang, Chi-Ho Kim, Jae-Geun Oh
  • Patent number: 11952490
    Abstract: The present disclosure relates to a polycarbonate resin composition, and more particularly, to a polycarbonate resin composition containing 90 wt % to 99 wt % of a polycarbonate resin, 0.3 wt % to 0.7 wt % of an anthraquinone-based black dye, and 0.2 wt % to 1.0 wt % of an acrylic polymeric chain extender, and a molded article containing the same.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: April 9, 2024
    Assignees: HYUNDAI MOBIS CO., LTD., LG CHEM, LTD.
    Inventors: Hyoung Taek Kang, Keun Hyung Lee, Young Min Kim, Moo Seok Lee, Myeung Il Kim, Jae Chan Park
  • Publication number: 20240114221
    Abstract: A camera module includes a housing, a reflective member positioned in the housing and changing a direction of light to a direction of an optical axis, a carrier carrying the reflective member and rotatable about a first axis with respect to the housing, and a first ball group disposed between the housing and the carrier, wherein the first ball group includes a main ball member providing the first axis of the carrier, and an auxiliary ball member disposed away from the first axis, and one or both of the housing and the carrier partially accommodates the auxiliary ball member, and includes an auxiliary guide groove extended in a circumferential direction of the first axis.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 4, 2024
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Hwan KWON, Nam Ki PARK, Young Bok YOON, Soon Seok KANG, Jae Won JUNG
  • Publication number: 20240107795
    Abstract: A substrate for a display, according to one embodiment, comprises: one surface; another surface which is the reverse of the one surface; a first area; and second areas, wherein the one surface is folded so as to face itself, the first area is defined as a folding area, and the second areas are defined as unfolding areas. The substrate for a display comprises a first layer, and a second layer which is disposed on the first layer, wherein the first area of the first layer comprises a plurality of first holes or first grooves, the first layer is an etch layer, and the second layer is an etch stopper layer.
    Type: Application
    Filed: December 4, 2023
    Publication date: March 28, 2024
    Inventors: Sung Won KANG, Jae Seok Park
  • Publication number: 20240105314
    Abstract: A computing apparatus includes: at least one memory; and at least one processor, wherein the processor generates quantitative information regarding at least one cell included in a region of interest of a pathological slide image by analyzing the pathological slide image, generates qualitative information regarding at least one tissue included in the pathological slide image by analyzing the pathological slide image, and controls a display apparatus to output at least one of the quantitative information and the qualitative information on the pathological slide image according to a manipulation of a user.
    Type: Application
    Filed: December 7, 2023
    Publication date: March 28, 2024
    Applicant: LUNIT INC.
    Inventors: Jeong Seok KANG, Jae Hong AUM, Dong Geun YOO, Tai Won CHUNG
  • Publication number: 20240094601
    Abstract: A camera module includes a housing, a movable body configured to move in a direction of an optical axis of the housing; a reinforcing member formed integrally on one surface of the movable body, and configured to increase a rigidity of the movable body; and a first buffer member formed in the reinforcing member, and configured to reduce an impactive force between the housing and the movable body.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Hyuk LEE, Soo Cheol LIM, Byung Woo KANG, Young Bok YOON, Jong Woo HONG, Jung Seok LEE
  • Patent number: 11935703
    Abstract: A multilayer electronic component has a body and a non-conductive resin layer. The non-conductive resin layer includes a body cover portion disposed in a region of an external surface of the body in which an electrode layer of an external electrode is not disposed, and an extending portion extending from the body cover portion between the electrode layer and a conductive resin layer of the external electrode, to thereby suppress arc discharge, improve bending strength, and improve moisture resistance.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Seok Yi, Jung Min Kim, Bon Seok Koo, Chang Hak Choi, Il Ro Lee, Byung Woo Kang, San Kyeong, Hae Sol Kang
  • Publication number: 20240081132
    Abstract: A window includes a window base layer, a high refractive layer disposed on the window base layer, a low refractive layer including hollow silica particles and disposed on the high refractive layer, and a primer coating layer disposed on the low refractive layer. Each of the low refractive layer and the primer coating layer has a refractive index in a range of about 1.4 to about 1.46. The low refractive layer has a thickness in a range of about 50 nm to about 80 nm.
    Type: Application
    Filed: May 23, 2023
    Publication date: March 7, 2024
    Inventors: BYOUNG DAE YE, SU-HYOUNG KANG, MYUNG-SEOK KWON, JAE SUL AN, JUYOUNG YOON, JAEWOO IM
  • Publication number: 20240077909
    Abstract: A display device according to an embodiment comprises: an elastic member; and at least one panel from among a display panel and a touch panel which are arranged on the elastic member, wherein the elastic member includes one surface and the other surface opposite to the one surface, the elastic member includes a first area and a second area, the first area is defined as a folding area, the second area is defined as an unfolding area, the elastic member has a plurality of first grooves arranged on the one surface in the first area thereof, and the panel is arranged on the other surface of the elastic member via an adhesive layer.
    Type: Application
    Filed: October 31, 2023
    Publication date: March 7, 2024
    Inventors: Sung Won KANG, Jae Seok PARK
  • Publication number: 20240075318
    Abstract: The present disclosure relates to a method for carrying out dose delivery quality assurance for high-precision radiation treatment, in which parameters affecting a pass rate of dose delivery quality assurance can be derived through regression analysis, which is a known statistical analysis method, and a pass rate prediction model capable of predicting each parameter and the pass rate of dose delivery quality assurance can be derived, and accordingly, it can be predicted in advance whether dose delivery quality assurance will be passed according to the parameters through the above prediction model, without repeatedly carrying out dose delivery quality assurance according to a patient's treatment plan, and as a result, the efficiency of dose delivery quality assurance can be enhanced, and the time or capacity required for such quality assurance is reduced, such that radiation treatment for an actual patient can be quickly and precisely carried out.
    Type: Application
    Filed: December 22, 2021
    Publication date: March 7, 2024
    Inventors: Young Nam KANG, Ji Na KIM, Hong Seok JANG, Byung Ock CHOI, Yun Ji SEOL, Tae Geon OH, Na Young AN, Jae Hyeon LEE, Kyu Min HAN, Ye Rim SHIN
  • Patent number: 11918781
    Abstract: An infusion flow regulator includes: a main body having an inlet through which fluid is introduced and an outlet through which the fluid is discharged; and a rotary dial rotatably coupled to the main body, with a sealing member interposed therebetween, so as to regulate a flow rate of the fluid, in which the rotary dial includes a regulating flow path having a shape of a recessed groove in cross section with a first width and a first height, and the regulating flow path includes a first region in which the first width is constant and the first height is decreased, and a second region in which both the first width and the first height are decreased. By the aforementioned configuration, the infusion flow regulator for the fluid can accurately regulate the flow rate even in a region where the flow rate of the fluid is very small.
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: March 5, 2024
    Assignee: Korea Aerospace Research Institute
    Inventors: Poo Min Park, Hyung Mo Kim, Tae Choon Park, Young Seok Kang, Jae Sung Huh, Doo Yong Lee
  • Patent number: 10916325
    Abstract: A memory chip includes a memory region group including a plurality of memory regions. The memory chip also includes a peripheral unit configured to generate region flags of the memory regions by performing write and read operations on the respective memory regions, each of the region flags indicating whether corresponding memory region is a defective region, and to generate a group flag indicating whether the memory region group needs to be repaired, based on the region flags.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: February 9, 2021
    Assignee: SK hynix Inc.
    Inventor: Jae Seok Kang
  • Patent number: 10643731
    Abstract: A semiconductor memory apparatus includes a test decoding select circuit. The test decoding selective circuit is configured to generate a normal decoding enable signal, a redundancy decoding enable signal, and a dummy decoding enable signal, in response to a test entry signal, a test code, and an active signal.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: May 5, 2020
    Assignee: SK hynix Inc.
    Inventor: Jae Seok Kang
  • Patent number: 10535402
    Abstract: A resistance variable memory apparatus includes a memory cell array region and a peripheral region disposed along an edge of the memory cell region. The memory cell array region may have a plurality of memory banks each of which includes at least one memory block. The resistance variable memory apparatus may include a data transmission block transmitting data between the plurality of memory banks and the peripheral region. The data transmission block includes a plurality of lower global input/output lines shared by pairs of adjacent memory banks, a plurality of lower multiplexers receiving data from pairs of adjacent lower global input/output lines and outputting data inputted from one of the lower global input/output lines, and an upper multiplexer receiving data output from the plurality of lower multiplexers and outputting data input from one of the lower multiplexers.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: January 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Jae Seok Kang
  • Publication number: 20190279734
    Abstract: A memory chip includes a memory region group including a plurality of memory regions. The memory chip also includes a peripheral unit configured to generate region flags of the memory regions by performing write and read operations on the respective memory regions, each of the region flags indicating whether corresponding memory region is a defective region, and to generate a group flag indicating whether the memory region group needs to be repaired, based on the region flags.
    Type: Application
    Filed: October 22, 2018
    Publication date: September 12, 2019
    Inventor: Jae Seok KANG
  • Patent number: 10400479
    Abstract: The present disclosure relates to a door lock device, and more specifically, to a backset adjustable door zoom up latch capable of adjusting a backset distance according to a variety of backset standards of the door, and a digital door lock device having the same. Accordingly, the backset adjustable locking device according to the present disclosure includes a latch, a holder inserted into the latch, an elastic member installed between the latch and the holder, and a zoom guide inserted into the latch and fastened with the holder to fix the latch to the holder.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: September 3, 2019
    Assignee: Jae-Seok Kang
    Inventor: Jae-Seok Kang
  • Patent number: 10312287
    Abstract: A semiconductor apparatus may include a first circuit forming region formed over a substrate, a first interlayer dielectric layer formed over the first circuit forming region, a first metal layer formed over the first interlayer dielectric layer, a second interlayer dielectric layer formed over the first metal layer, and a second circuit forming region formed over the second interlayer dielectric layer. A first circuit and a second circuit that are included in the first circuit forming region and a third circuit that is included in the second circuit forming region may be electrically coupled to each other.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 4, 2019
    Assignee: SK hynix Inc.
    Inventor: Jae Seok Kang
  • Publication number: 20190164622
    Abstract: A semiconductor memory apparatus includes a test decoding select circuit. The test decoding selective circuit is configured to generate a normal decoding enable signal, a redundancy decoding enable signal, and a dummy decoding enable signal, in response to a test entry signal, a test code, and an active signal.
    Type: Application
    Filed: October 23, 2018
    Publication date: May 30, 2019
    Applicant: SK hynix Inc.
    Inventor: Jae Seok KANG
  • Patent number: 10176885
    Abstract: A semiconductor memory apparatus includes a comparison circuit generating a detection code in response to stored data and expected data, a counting circuit generating a counting code in response to the detection code, a selection code output circuit outputting one of a plurality of expected codes as a selection code in response to a selection signal, and a plurality of signal storage circuits. A comparison result output circuit including a plurality of signal storage circuits which stores a comparison result of a comparison between the counting code and the selection code in one signal storage circuit among the plurality of signal storage circuits according to the selection signal, and a value stored in one signal storage circuit among the plurality of signal storage circuits is output as a result signal in response to an output enable signal.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: January 8, 2019
    Assignee: SK hynix Inc.
    Inventor: Jae Seok Kang