Patents by Inventor Jae Sung Roh
Jae Sung Roh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240045453Abstract: The present inventive concept relates to a gas supply apparatus for a substrate processing apparatus, the gas supply apparatus comprising: a first supply line connected to a first gas spray unit; a plurality of first gas supply devices connected to the first supply line; a first measurement device measuring a first pressure at the first supply line; a second supply line connected to a second gas spray unit; a plurality of second gas supply devices connected to the second supply line; and a second measurement device measuring a second pressure at the second supply line, wherein the first measurement device checks if the first pressure deviates from a first reference value, and the second measurement device checks if the second pressure deviates from a second reference value.Type: ApplicationFiled: January 12, 2022Publication date: February 8, 2024Inventors: Se Whan JIN, Jae Sung ROH, Hong Min YOON, Hong Soo YOON, Youn Joo JANG, Byoung Ha CHO, Ji Hyun CHO
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Publication number: 20230323533Abstract: The present inventive concept relates to a substrate processing method in which a processing process is performed on a substrate in a processing space divided into a first processing region and a second processing region. The substrate processing method comprises the steps of: performing a first processing process on a substrate in the first processing region when the substrate supported by the support part is positioned in the first processing region; moving the substrate to the second processing region by rotating the support part when the first processing process is completed; and performing a second processing process on the substrate in the second processing region when the substrate supported by the support part is positioned in the second processing region.Type: ApplicationFiled: September 24, 2021Publication date: October 12, 2023Inventors: Se Whan JIN, Jae Sung ROH, Cheong SON, Hong Min YOON, Hong Soo YOON, Youn Joo JANG, Byoung Ha CHO, Ji Hyun CHO
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Publication number: 20230235457Abstract: The present inventive concept is a substrate processing method in which processing steps are carried out on a substrate supported on a support unit in a processing space that is divided into a first processing area and a second processing area, the substrate processing method comprising: a step in which a first gas and a first purge gas are sprayed in the first processing area; and a step in which a second purge gas and a second gas are sequentially sprayed in the second processing area.Type: ApplicationFiled: May 17, 2021Publication date: July 27, 2023Inventors: Cheong SON, Jae Sung ROH, Hong Min YOON, Hong Soo YOON, Youn Joo JANG, Ji Hyun CHO, Se Whan JIN, Chul Joo HWANG
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Patent number: 9831085Abstract: Provided are a method of fabricating a hafnium oxide layer and a method of fabricating a semiconductor device using the same. The method of fabricating a tetragonal hafnium oxide layer includes providing a substrate and then forming an initial hafnium oxide layer on the substrate. The initial hafnium oxide layer may have an amorphous structure, a monoclinic crystal structure, or a mixed structure thereof on the substrate. Phase-changing the initial hafnium oxide layer to a tetragonal hafnium oxide layer by heating the initial hafnium oxide layer at a temperature equal to or higher than a phase change temperature to the tetragonal hafnium oxide layer, is performed. Then, the heated tetragonal hafnium oxide layer may be rapidly cooled to suppress nucleation and growth of a monoclinic hafnium oxide in the tetragonal hafnium oxide layer.Type: GrantFiled: July 1, 2016Date of Patent: November 28, 2017Assignee: SK Hynix Inc.Inventors: Deok Sin Kil, Jae Sung Roh
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Publication number: 20170004967Abstract: Provided are a method of fabricating a hafnium oxide layer and a method of fabricating a semiconductor device using the same. The method of fabricating a tetragonal hafnium oxide layer includes providing a substrate and then forming an initial hafnium oxide layer on the substrate. The initial hafnium oxide layer may have an amorphous structure, a monoclinic crystal structure, or a mixed structure thereof on the substrate. Phase-changing the initial hafnium oxide layer to a tetragonal hafnium oxide layer by heating the initial hafnium oxide layer at a temperature equal to or higher than a phase change temperature to the tetragonal hafnium oxide layer, is performed. Then, the heated tetragonal hafnium oxide layer may be rapidly cooled to suppress nucleation and growth of a monoclinic hafnium oxide in the tetragonal hafnium oxide layer.Type: ApplicationFiled: July 1, 2016Publication date: January 5, 2017Inventors: Deok Sin KIL, Jae Sung ROH
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Patent number: 9214467Abstract: A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer.Type: GrantFiled: January 23, 2015Date of Patent: December 15, 2015Assignee: SK Hynix Inc.Inventors: Jin-Hyock Kim, Seung-Jin Yeom, Ki-Seon Park, Han-Sang Song, Deok-Sin Kil, Jae-Sung Roh
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Publication number: 20150132916Abstract: A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer.Type: ApplicationFiled: January 23, 2015Publication date: May 14, 2015Inventors: Jin-Hyock KIM, Seung-Jin YEOM, Ki-Seon PARK, Han-Sang SONG, Deok-Sin KIL, Jae-Sung ROH
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Patent number: 8946047Abstract: A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer.Type: GrantFiled: June 4, 2010Date of Patent: February 3, 2015Assignee: SK Hynix Inc.Inventors: Jin-Hyock Kim, Seung-Jin Yeom, Ki-Seon Park, Han-Sang Song, Deok-Sin Kil, Jae-Sung Roh
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Patent number: 8298909Abstract: A capacitor includes a lower electrode, a dielectric layer, an upper electrode, and a ruthenium oxide layer. At least one of the lower electrode and the upper electrode is formed of a ruthenium layer, and the ruthenium oxide layer is disposed next to the ruthenium layer.Type: GrantFiled: December 27, 2007Date of Patent: October 30, 2012Assignee: Hynix Semiconductor Inc.Inventors: Kwan-Woo Do, Jae-Sung Roh, Kee-Jeung Lee, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kyung-Woong Park, Han-Sang Song
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Patent number: 8134195Abstract: A semiconductor device, and a method of fabricating the semiconductor device, which is able to prevent a leaning phenomenon from occurring between the adjacent storage nodes. The method includes forming a plurality of multi-layered pillar type storage nodes each of which is buried in a plurality of mold layers, wherein the uppermost layers of the multi-layered pillar type storage nodes are fixed by a support layer, etching a portion of the support layer to form an opening, and supplying an etch solution through the opening to remove the multiple mold layers. A process of depositing and etching the mold layer by performing the process 2 or more times to form the multi-layered pillar type storage node. Thus, the desired capacitance is sufficiently secured and the leaning phenomenon is avoided between adjacent storage nodes.Type: GrantFiled: December 30, 2008Date of Patent: March 13, 2012Assignee: Hynix Semiconductor Inc.Inventors: Kee-Jeung Lee, Jae-Sung Roh, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kwan-Woo Do, Kyung-Woong Park, Jeong-Yeop Lee
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Patent number: 8120180Abstract: A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug fainted on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug.Type: GrantFiled: July 16, 2010Date of Patent: February 21, 2012Assignee: Hynix Semiconductor Inc.Inventors: Jin-Hyock Kim, Jae-Sung Roh, Seung-Jin Yeom, Kee-Jeung Lee, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim
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Patent number: 8048758Abstract: A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. A sacrificial pattern is formed over the isolation layer and covers the cell region. The isolation layer is etched in the peripheral region to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed.Type: GrantFiled: March 22, 2011Date of Patent: November 1, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae-Sung Roh, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
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Patent number: 8048757Abstract: A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial pattern is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer in the peripheral region is etched to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed.Type: GrantFiled: March 22, 2011Date of Patent: November 1, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae-Sung Roh, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
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Patent number: 8017491Abstract: A method for fabricating a capacitor includes forming a sacrificial layer having a plurality of trenches on an upper portion of a substrate, forming storage nodes in the trenches, exposing upper portions of the storage nodes by removing a portion of the sacrificial layer, forming supporters to support the exposed upper portions of the storage nodes, removing the sacrificial layer under the supporters, and removing the supporters.Type: GrantFiled: December 27, 2007Date of Patent: September 13, 2011Assignee: Hynix Semiconductor Inc.Inventors: Kee-Jeung Lee, Jae-Sung Roh, Seung-Jin Yeom, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kwan-Woo Do
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Publication number: 20110171807Abstract: A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial pattern is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer in the peripheral region is etched to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed.Type: ApplicationFiled: March 22, 2011Publication date: July 14, 2011Applicant: Hynix Semiconductor Inc.Inventors: Jae-Sung Roh, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
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Publication number: 20110171808Abstract: A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. A sacrificial pattern is formed over the isolation layer and covers the cell region. The isolation layer is etched in the peripheral region to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed.Type: ApplicationFiled: March 22, 2011Publication date: July 14, 2011Applicant: Hynix Semiconductor Inc.Inventors: Jae-Sung ROH, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
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Patent number: 7910452Abstract: A method for fabricating a capacitor includes forming an isolation layer over a substrate. The isolation layer forms a plurality of open regions. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial layer is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer and the sacrificial layer are then removed.Type: GrantFiled: June 29, 2007Date of Patent: March 22, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae-Sung Roh, Kee-Jeung Lee, Han-Sang Song, Seung-Jin Yeom, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim
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Patent number: 7888245Abstract: A plasma doping method includes providing a doping source over a substrate. The doping source includes dopants that are to be injected into the substrate. At least two different bias voltages are applied to inject the dopants from the doping source to the substrate.Type: GrantFiled: May 3, 2007Date of Patent: February 15, 2011Assignee: Hynix Semiconductor Inc.Inventors: Jae-Sung Roh, Jae-Geun Oh, Hyun-Chul Sohn, Sun-Hwan Hwang, Jin-Ku Lee
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Patent number: 7835134Abstract: A capacitor includes a lower electrode, a dielectric structure over the lower electrode, the dielectric structure including at least one crystallized zirconium oxide (ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer, and an upper electrode formed over the dielectric structure. A method for fabricating a capacitor includes forming a lower electrode over a certain structure, forming a dielectric structure including at least one crystallized zirconium oxide (ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer over the lower electrode, and forming an upper electrode over the dielectric structure.Type: GrantFiled: September 29, 2009Date of Patent: November 16, 2010Assignee: Hynix Semiconductor Inc.Inventors: Deok-Sin Kil, Han-Sang Song, Seung-Jin Yeom, Ki-Seon Park, Jae-Sung Roh
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Publication number: 20100276804Abstract: A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a first plug filled in a portion of the contact hole, a diffusion barrier layer formed above the first plug and in a bottom portion and on sidewalls of a remaining portion of the contact hole, a second plug fainted on the diffusion barrier layer and filled in the contact hole, and a storage node coupled to and formed on the second plug.Type: ApplicationFiled: July 16, 2010Publication date: November 4, 2010Inventors: Jin-Hyock KIM, Jae-Sung Roh, Seung-Jin Yeom, Kee-Jeung Lee, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim