Abstract: A nonvolatile memory device may include a plurality of memory blocks. The nonvolatile memory device may include a controller configured to perform an erase operation by repeating an erase loop, and may generate and store a test result based on a pass erase loop count of the erase operation in response to a result processing command. The erase loop may include applying an erase voltage to a target memory block among the memory blocks in response to an erase command.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.

Abstract: A semiconductor memory device includes memory blocks including pages connected to plural main cells, a spare block, including pages connected to spare cells, configured to store a random seed for randomization to the spare cells connected to each page, page buffers configured to scramble data inputted for program operation by using random seed read from a page of the spare block selected by a control signal to transmit the scrambled data to the bit line, and configured to descramble data read from a main cell selected for read operation and output the descrambled data, and a controller configured to output the control signal to select a page of the spare block corresponding to an address of a page of the memory block selected for the programming or reading, and configured to control a scramble operation and a descramble operation of the page buffers.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.

Abstract: A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.

Abstract: A nonvolatile memory device includes: N (N is an integer equal to or greater than 2) number of nonvolatile memory cells disposed in a flag area of a page, N number of flag page buffers configured to input and output flag data to and from the nonvolatile memory cells of the flag area, and a data input/output control unit configured to select R number of flag page buffers so that the flag data is inputted and outputted from the R selected flag page buffers and no flag data is inputted and outputted through unselected N-R number of flag page buffers, wherein no one flag page buffer of the R selected flag page buffers is immediately adjacent to another one of the R selected flag page buffers.

Abstract: A semiconductor memory device comprises a memory cell array including a plurality of memory blocks each including a plurality of pages, wherein each of the plurality of pages includes at least one flag cell indicating whether data is in a corresponding page, and a peripheral circuit configured to read data of flag cells of a selected memory block in response to an erase request and to omit an erase operation on the selected memory block based on the data of the flag cells.

Abstract: A semiconductor memory device includes memory blocks including pages connected to plural main cells, a spare block, including pages connected to spare cells, configured to store a random seed for randomization to the spare cells connected to each page, page buffers configured to scramble data inputted for program operation by using random seed read from a page of the spare block selected by a control signal to transmit the scrambled data to the bit line, and configured to descramble data read from a main cell selected for read operation and output the descrambled data, and a controller configured to output the control signal to select a page of the spare block corresponding to an address of a page of the memory block selected for the programming or reading, and configured to control a scramble operation and a descramble operation of the page buffers.

Abstract: A nonvolatile memory device includes: N (N is an integer equal to or greater than 2) number of nonvolatile memory cells disposed in a flag area of a page, N number of flag page buffers configured to input and output flag data to and from the nonvolatile memory cells of the flag area, and a data input/output control unit configured to select R number of flag page buffers so that the flag data is inputted and outputted from the R selected flag page buffers and no flag data is inputted and outputted through unselected N?R number of flag page buffers, wherein no one flag page buffer of the R selected flag page buffers is immediately adjacent to another one of the R selected flag page buffers.

Abstract: A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in the memory cell or reading data from the memory cell, a controller configured to control the page buffer circuit so that the initial data stored in the memory cell array are read when operation of the flash memory device is started, discriminate error of the read initial data, and amend the error of the initial data, and an initial data latching circuit for latching the initial data of which the error is amended by the controller.

Abstract: A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.

Abstract: A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder.

Abstract: A semiconductor memory device can improve electrical properties by prohibiting a leakage current, which flows through a memory cell, in such a way as to turn off a drain select transistor, a source select transistor and a side transistor of an unselected memory cell block when the semiconductor memory device operates. The semiconductor memory device includes a memory cell block in which a plurality of memory cells, drain and source select transistors, and side word line transistors are connected in a string structure, a block decoder for outputting a block select signal in response to predecoded address signals and controlling the drain and source select transistors and the side word line transistors, and a block switch for connecting a global word line to word lines of the memory cell block in response to the block select signal.

Abstract: A method of testing for a leakage current between bit lines of a nonvolatile memory device includes providing the nonvolatile memory device with a page buffer having first and second bit lines coupled thereto, precharging the first bit line to a first voltage, supplying a second voltage to the second bit line, floating the second bit line and evaluating the second bit line for a set time period, and detecting a voltage level of the second bit line and outputting a test result of testing for the leakage current between the first and second bit lines by the page buffer.

Abstract: A method includes performing test bit setting; programming a first page using data set by the test bit setting, and storing a fail status bit in a page buffer, which is connected to a first bit line having a fail status, based on a verification result of the test program; performing a test program and verification on a second page based on a test program and fail status bit storage result of a preceding page, and storing a fail status bit in the page buffer, which is connected to a second bit line having a fail status, based on a verification result of the test program and verification; and after a test program, verification, and fail status bit setting with respect to the entire pages of a memory block are completed, outputting data of the page buffer.

Abstract: A method of programming a multi level cell in a non-volatile memory device includes: performing a program operation on main cells and indicator cells; performing a first verifying operation on the main cells and the indicator cells based on a first verifying voltage; performing repeatedly the program operation and the first verifying operation until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage; and performing a second verifying operation on the main cells and the indicator cells based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage.

Abstract: A method of programming a multi level cell in a non-volatile memory device includes: performing a program operation on main cells and indicator cells; performing a first verifying operation on the main cells and the indicator cells based on a first verifying voltage; performing repeatedly the program operation and the first verifying operation until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage; and performing a second verifying operation on the main cells and the indicator cells based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage.

Abstract: A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder.

Abstract: A method of testing for a leakage current between bit lines of a nonvolatile memory device includes providing the nonvolatile memory device with a page buffer having first and second bit lines coupled thereto, precharging the first bit line to a first voltage, supplying a second voltage to the second bit line, floating the second bit line and evaluating the second bit line for a set time period, and detecting a voltage level of the second bit line and outputting a test result of testing for the leakage current between the first and second bit lines by the page buffer.