Abstract: A NLRP3-inhibitory compound 7 (NIC7) and a potent derivative NIC7w are disclosed. NLRP3-inhibitory compound 7 (NIC7) and a potent derivative NIC7w are a novel small-molecule inhibitor for inhibiting NLRP3 inflammasomes are identified. These compounds inhibit main elements of the NLRP3 signaling pathway, primarily IL-1? and caspase 1, and improve cognitive behaviors of mice in Alzheimer disease mouse models. Compositions of NIC7 and NIC7w are suitable as a therapeutic agent in treating, preventing, or improving the conditions of Alzheimer's disease.

Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.

Abstract: In a method, an isolation layer pattern is formed on a substrate to define first and second active fins. An ARC layer is formed on the isolation layer pattern to at least partially cover sidewalls of the first and second active fins. A level of a top surface of the ARC layer is equal to or less than, and equal to or greater than half of, those of the first and second active fins. A photoresist layer is formed on the first and second active fins and the ARC layer. A portion of the photoresist layer is removed to form a photoresist pattern covering the first active fin and exposing the second active fin. A portion of the ARC layer under the removed portion of the photoresist layer is removed to form an ARC layer pattern. Impurities are implanted into the exposed second active fin to form an impurity region.

Abstract: In a method of manufacturing a semiconductor device, an isolation layer pattern is formed on a substrate to define a field region covered by the isolation layer pattern and first and second active regions that is not covered by the isolation layer pattern and protrudes from the isolation layer pattern. A first anti-reflective layer is formed on the isolation layer pattern. A first photoresist layer is formed on the first and second active regions of the substrate and the first anti-reflective layer. The first photoresist layer is partially etched to form a first photoresist pattern covering the first active region. Impurities are implanted into the second active region to form a first impurity region.

Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.

Abstract: In a method, an isolation layer pattern is formed on a substrate to define first and second active fins. An ARC layer is formed on the isolation layer pattern to at least partially cover sidewalls of the first and second active fins. A level of a top surface of the ARC layer is equal to or less than, and equal to or greater than half of, those of the first and second active fins. A photoresist layer is formed on the first and second active fins and the ARC layer. A portion of the photoresist layer is removed to form a photoresist pattern covering the first active fin and exposing the second active fin. A portion of the ARC layer under the removed portion of the photoresist layer is removed to form an ARC layer pattern. Impurities are implanted into the exposed second active fin to form an impurity region.

Abstract: Example embodiments relate to an overlay measurement device and method of forming an overlay pattern. The overlay measurement device includes a tray part with a substrate having a first region and a second region, a measurement part which measures an overlay of a first or second element, and a processor part which receives data measured by the measurement part and corrects the position of the first or second element, wherein the substrate comprises a first layer comprising the first overlay marks, a second layer comprising the second overlay marks, which intersects the first direction, in the second region and not comprising overlay marks which are used to measure the overlay of the second element; and the photoresist pattern which is formed on the first and second layers and overlaps the first and second overlay marks.

Abstract: In a method of manufacturing a semiconductor device, an isolation layer pattern is formed on a substrate to define a field region covered by the isolation layer pattern and first and second active regions that is not covered by the isolation layer pattern and protrudes from the isolation layer pattern. A first anti-reflective layer is formed on the isolation layer pattern. A first photoresist layer is formed on the first and second active regions of the substrate and the first anti-reflective layer. The first photoresist layer is partially etched to form a first photoresist pattern covering the first active region. Impurities are implanted into the second active region to form a first impurity region.

Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.