Patents by Inventor Jaeyeol Song
Jaeyeol Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990473Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.Type: GrantFiled: April 19, 2022Date of Patent: May 21, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Jaeyeol Song, Seungha Oh, Rakhwan Kim, Minjung Park, Dongsoo Lee
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Patent number: 11987561Abstract: A resist underlayer composition includes (A) a polymer including a structural unit represented by Chemical Formula 1, a compound represented by Chemical Formula 2, or a combination thereof; (B) a polymer including a structure in which at least one moiety represented by Chemical Formula 3 or Chemical Formula 4 and a moiety represented by Chemical Formula 7 are bound to each other; and (C) a solvent:Type: GrantFiled: January 12, 2021Date of Patent: May 21, 2024Assignee: Samsung SDI Co., Ltd.Inventors: Yoojeong Choi, Soonhyung Kwon, Hyeon Park, Jaeyeol Baek, Minsoo Kim, Shinhyo Bae, Daeseok Song, Dowon Ahn
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Publication number: 20230402523Abstract: A semiconductor device includes first and second active patterns respectively provided on a first and second PMOSFET regions of a substrate, a first channel pattern on the first active pattern, the first channel pattern including first semiconductor patterns stacked and spaced apart from each other, a second channel pattern on the second active pattern, the second channel pattern including second semiconductor patterns stacked and spaced apart from each other, a first gate electrode on the first channel pattern, and a second gate electrode on the second channel pattern. A first concentration of aluminum (Al) or silicon (Si) in an inner gate electrode of the first gate electrode is different from a second concentration of aluminum (Al) or silicon (Si) in an inner gate electrode of the second gate electrode.Type: ApplicationFiled: January 31, 2023Publication date: December 14, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jaeyeol SONG, Ohseong Kwon, Suyoung Bae, Sangyong Kim
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Publication number: 20230361121Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.Type: ApplicationFiled: July 17, 2023Publication date: November 9, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Dongsoo LEE, Wonkeun CHUNG, Hoonjoo NA, Suyoung BAE, Jaeyeol SONG, Jonghan LEE, HyungSuk JUNG, Sangjin HYUN
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Patent number: 11742351Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.Type: GrantFiled: July 26, 2021Date of Patent: August 29, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Dongsoo Lee, Wonkeun Chung, Hoonjoo Na, Suyoung Bae, Jaeyeol Song, Jonghan Lee, HyungSuk Jung, Sangjin Hyun
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Patent number: 11557656Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.Type: GrantFiled: September 18, 2020Date of Patent: January 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jonghan Lee, Wandon Kim, Jaeyeol Song, Jeonghyuk Yim, HyungSuk Jung
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Publication number: 20220302115Abstract: A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode.Type: ApplicationFiled: June 3, 2022Publication date: September 22, 2022Inventors: JONGHO PARK, JAEYEOL SONG, WANDON KIM, BYOUNGHOON LEE, MUSARRAT HASAN
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Publication number: 20220254779Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.Type: ApplicationFiled: April 19, 2022Publication date: August 11, 2022Inventors: Jaeyeol Song, Seungha Oh, Rakhwan Kim, Minjung Park, Dongsoo Lee
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Patent number: 11387236Abstract: A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode.Type: GrantFiled: April 6, 2020Date of Patent: July 12, 2022Inventors: Jongho Park, Jaeyeol Song, Wandon Kim, Byounghoon Lee, Musarrat Hasan
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Patent number: 11335680Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.Type: GrantFiled: June 25, 2020Date of Patent: May 17, 2022Inventors: Jaeyeol Song, Seungha Oh, Rakhwan Kim, Minjung Park, Dongsoo Lee
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Publication number: 20210358910Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.Type: ApplicationFiled: July 26, 2021Publication date: November 18, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Dongsoo LEE, Wonkeun CHUNG, Hoonjoo NA, Suyoung BAE, Jaeyeol SONG, Jonghan LEE, HyungSuk JUNG, Sangjin HYUN
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Patent number: 11121131Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.Type: GrantFiled: October 3, 2019Date of Patent: September 14, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Dongsoo Lee, Wonkeun Chung, Hoonjoo Na, Suyoung Bae, Jaeyeol Song, Jonghan Lee, HyungSuk Jung, Sangjin Hyun
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Publication number: 20210151432Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.Type: ApplicationFiled: June 25, 2020Publication date: May 20, 2021Inventors: Jaeyeol Song, Seungha Oh, Rakhwan Kim, Minjung Park, Dongsoo Lee
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Publication number: 20210082917Abstract: A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode.Type: ApplicationFiled: April 6, 2020Publication date: March 18, 2021Inventors: JONGHO PARK, JAEYEOL SONG, WANDON KIM, BYOUNGHOON LEE, MUSARRAT HASAN
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Publication number: 20210005729Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.Type: ApplicationFiled: September 18, 2020Publication date: January 7, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: JONGHAN LEE, WANDON KIM, JAEYEOL SONG, JEONGHYUK YIM, HYUNGSUK JUNG
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Patent number: 10811505Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.Type: GrantFiled: May 29, 2018Date of Patent: October 20, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jonghan Lee, Wandon Kim, Jaeyeol Song, Jeonghyuk Yim, HyungSuk Jung
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Publication number: 20200035678Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.Type: ApplicationFiled: October 3, 2019Publication date: January 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Dongsoo LEE, Wonkeun Chung, Hoonjoo Na, Suyoung Bae, Jaeyeol Song, Jonghan Lee, HyungSuk Jung, Sangjin Hyun
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Patent number: 10461167Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.Type: GrantFiled: January 4, 2018Date of Patent: October 29, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Dongsoo Lee, Wonkeun Chung, Hoonjoo Na, Suyoung Bae, Jaeyeol Song, Jonghan Lee, HyungSuk Jung, Sangjin Hyun
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Publication number: 20190165114Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.Type: ApplicationFiled: May 29, 2018Publication date: May 30, 2019Inventors: JONGHAN LEE, WANDON KIM, JAEYEOL SONG, JEONGHYUK YIM, HyungSuk JUNG
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Publication number: 20180374926Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.Type: ApplicationFiled: January 4, 2018Publication date: December 27, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: DONGSOO LEE, WONKEUN CHUNG, HOONJOO NA, SUYOUNG BAE, JAEYEOL SONG, JONGHAN LEE, HYUNGSUK JUNG, SANGJIN HYUN