Abstract: Techniques are disclosed related to determining a modulation quality measurement of a device-under-test (DUT). A modulated signal is received from a source a plurality of times, and each received modulated signal is transmitted to each of a first vector signal analyzer (VSA) and a second VSA. The first VSA and the second VSA demodulate the received modulated signals to produce first error vectors and second error vectors, respectively. A cross-correlation calculation is performed on the first error vectors and second error vectors of respective received modulated signals to produce a cross-correlation measurement, and the cross-correlation measurement is averaged over the plurality of received modulated signals. A modulation quality measurement is determined based on the averaged cross-correlation measurement.

Abstract: Dynamic characterization of complex high-order nonlinearity in transmitter (TX) and receiver (RX) signal chains of transceiver systems can be efficiently and accurately performed. A loopback connection may be used to facilitate self-characterization. Appropriate RX and TX configuration settings may be developed to facilitate de-coupling of individual RX and TX nonlinearities from measured cascade nonlinearity. The system's high-order response to a two-tone signal generation may be measured, and complex mathematical analysis may be performed to identify and isolate passband nonlinear components to extract a high-order memory-less model for the system. The extracted system model may be used in the corrective and non-iterative pre-distortion of generated signals and in the post-distortion of received signals to improve linearity performance of the transceiver.

Abstract: Dynamic characterization of complex high-order nonlinearity in transmitter (TX) and receiver (RX) signal chains of transceiver systems can be efficiently and accurately performed. A loopback connection may be used to facilitate self-characterization. Appropriate RX and TX configuration settings may be developed to facilitate de-coupling of individual RX and TX nonlinearities from measured cascade nonlinearity. The system's high-order response to a two-tone signal generation may be measured, and complex mathematical analysis may be performed to identify and isolate passband nonlinear components to extract a high-order memory-less model for the system. The extracted system model may be used in the corrective and non-iterative pre-distortion of generated signals and in the post-distortion of received signals to improve linearity performance of the transceiver.

Abstract: Device and method for outputting a leaked radio frequency (RF) signal useable for triggering devices under test (DUTs). The device may include a vector signal analyzer (VSA) which may also perform the method for triggering DUTs. The VSA may include a first component, configured to generate an RF signal, an input configured to receive RF signals transmitted from DUTs, and a received RF signal conditioning portion, each coupled to an internal switching portion. The VSA may be configured to generate the RF signal via the first component, leak the RF signal from the first component to the internal switching portion, generating a leaked RF signal, route the leaked RF signal to the input, bypassing the received RF signal conditioning portion and output the leaked RF signal which is useable to trigger DUTs via the input.

Abstract: A counter circuit with multiple registers for eliminating reprogramming delays and for providing seamless switching between timing signals. In a first embodiment, two registers are preloaded with values and control logic chooses between the registers for loading a counter. The counter asserts a terminal count signal to output logic, which correspondingly asserts a convert pulse to an analog measuring circuit. The control logic receives start and stop signals and the terminal count signal, where the control logic controls operation accordingly. In this manner, a delay value is initially loaded into the counter to provide an initial delay period upon receiving the start signal, and then a scan rate value is continually loaded into the counter from another register thereafter for defining the scan rate until the start signal is received.

Abstract: A latency error detection circuit including two cascaded latches receiving a clock signal from a measuring system upon the occurrence of an event and correspondingly asserting a bit to a processing system, and a circuit for clearing the first latch after the processing system acknowledges detecting the bit being asserted. If the second latch is clocked before the first latch is cleared, the second latch sets an error bit indicating a latency error condition. The processor system monitors the error bit to determine whether a latency error has occurred.