Abstract: A system for transferring data files between a host device and a secondary device can include a bridge device forming at least a portion of the secondary device. The bridge device can have a de-multiplex (de-MUX) data path with an input coupled to a host interface (I/F), a first output coupled to a storage I/F and a second output coupled to a processor I/F. A controller circuit can have control inputs coupled to receive configuration commands from the processor I/F and control outputs coupled to control terminals of the de-MUX data path. The controller circuit enables and maintaining a data path between the host I/F and the first output of the de-MUX data path for a predetermined number of data transfers in response to at least a first configuration data input.

Abstract: A method and apparatus for configuring signal lines with idle codes is disclosed. According to one embodiment, data transmission system (100) may include encoders (112, 114, 116 and 118) that transmit data over signal line lanes (Lane 0 to Lane n). In an idle state, an encoder (112, 114, 116 and 118) may output one of at least two idle codes (IDLE A and IDLE B). One idle code (IDLE A) may indicate a first lane of a group of lanes. Another idle code (IDLE B) may indicate subsequent lanes of a group of lanes.

Abstract: An integrated circuit bridge device can include a first interface circuit coupled to a buffer circuit and a configurable in response to configuration information to receive command information, address information, and data values on a same multi-bit input/output (I/O) bus. A second interface circuit can be coupled to the buffer circuit and configured to communicate according to a first communication protocol different from that executable by the first interface circuit. In addition, a controller circuit formed in the same substrate as the first and second interface circuits can be configured to enable data transfers between the first interface circuit and the second interface circuits via the buffer circuit.

Abstract: An integrated circuit bridge device can include a first interface circuit coupled to a buffer circuit and configurable in response to configuration information to receive command information, address information, and data values on a same multi-bit input/output (I/O) bus. A second interface circuit can be coupled to the buffer circuit and configured to communicate according to a first communication protocol different from that executable by the first interface circuit. In addition, a controller circuit formed in the same substrate as the first and second interface circuits can be configured to enable data transfers between the third interface circuit and the first interface circuits via the buffer circuit.

Abstract: A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Abstract: A search engine method and apparatus can store and update status information for each entry of a content addressable memory (CAM) array, for a learn operation, or the like. A search engine can include a status memory block external to and independent of the CAM array. A status memory block (800) can include a number of memory sections (806-0 to 806-2) that each includes a number of bit locations for storing a free/not-free status of CAM entries in a hierarchical fashion. Corresponding control sections (808-0 to 808-2) can include priority encoders (812-0 to 812-2) that determine a first free element in a memory section for a next hierarchical level, as well as status aggregation logic (814-0 to 814-2) that can generate an aggregated status that is propagated to a previous hierarchical level.

Abstract: According to one embodiment, a content addressable memory (CAM) device (100) may include a number of segments (102 or 104). Search target compare circuits (110 and 112) can compare a target value TARGET to programmable information values (PIV0 and PIV1) associated with a particular segment (102 and 104). If a search target value TARGET matches a programmable information value (PIV0 and PIV1), search operations may be performed in a segment (102 or 104). If a search target value TARGET does not match a programmable information value, (PIV0 and PIV1), search operations may be prevented within a segment (102 or 104).

Abstract: A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Abstract: A method and apparatus for configuring signal lines with idle codes is disclosed. According to one embodiment, data transmission system (100) may include encoders (112, 114, 116 and 118) that transmit data over signal line lanes (Lane 0 to Lane n). In an idle state, an encoder (112, 114, 116 and 118) may output one of at least two idle codes (IDLE A and IDLE B). One idle code (IDLE A) may indicate a first lane of a group of lanes. Another idle code (IDLE B) may indicate subsequent lanes of a group of lanes.

Abstract: According to a data packet framing method of one embodiment, a data packet (100) may include a combination control character (102) that may convey framing information FLAG (102-0) and a code information CODE (102-1). Framing information FLAG (102-0) can indicate a start of a packet, and a code information CODE (102-1) can indicate another feature of a packet, such as size. A combination control character (102) may preferably be no larger than a data character of a data packet.

Abstract: According to one embodiment, a content addressable memory (CAM) device (100) may include a number of CAM entry sets (102-0 and 102-1), each of which includes multiple CAM entries. CAM (100) may also include multiple programmable information registers (PIRs) (104-0 and 104-1), each of which can be associated with a CAM entry set (102-0 and 102-1). PIRs (104-0 and 104-1) may be accessed in response to CAM commands. Values stores in PIRs (104-0 and 104-1) may control access to associated CAM entry sets (102-0 and 102-1) and/or be output in response to predetermined operations in an associated CAM entry set (102-0 and 102-1).

Abstract: A search engine system (100) and CAM device (300) are disclosed. A search engine system (100) may generate response packets (112) in response to requests packets (110) and include at least one content addressable memory (CAM) device (102-0) having an input interface (116-0) for receiving data packets and an output interface (116-1) for transmitting data packets.

Abstract: According to an embodiment, a content addressable memory (CAM) device (104) may be capable of executing a “restricted” search operation. A restricted search operation (an “explore” or “search beyond” operation) may compare only a portion of the CAM entries to a search key device. Preferably, a restricted search operation may restrict searches to entries having an index value greater than a received search index value.

Abstract: A method for assigning chip identification (ID) values is disclosed. Unique chip ID values may be assigned to chips (106-0 to 106-5) in a system (100) having multiple branches (112-0 and 112-1). After chip IDs have been assigned to chips of a first branch (112-0) a command processing system (104) may issue an end of branch indication. Chip IDs may then be assigned to chips of a next branch (112-1).

Abstract: According to one embodiment, a search engine device (100) may include an input (102), search portion (106), and a vote portion (108). A vote portion (108) may receive responses to a search request at inputs. According to precedence information in received responses, a vote portion (108) may generate an output response having its own precedence information.

Abstract: A content addressable memory (CAM) device (100) may include a CAM array (102), a CAM array access circuit (104), and a preclassifier circuit (106). A preclassifier circuit (106) may selectively modify portions of an input data value before such an input data value is applied to a CAM array (102). In particular embodiments, a preclassifier circuit (106) may compare a compare portion of an input data value to one or more ranges. If such a portion falls within a range, a preclassifier may substitute a compare portion with a range code value to form a modified input data value.

Abstract: A decoder circuit (100) is disclosed that may include “string” decoders (102-0 and 102-1), a compare circuit (104) and an enable circuit (106). String decoders (102-0 and 102-1) may provide “one-hot” or “string” decoding. One-hot decoding may activate one pre-decode signal. String decoding may activate one or more pre-decode signals. A compare circuit (104) may receive at least two pre-decode signals from one string decoder (102-1) and compare such values to generate a comparison result CMP. An enable circuit may generate decoder output signals (DEC0-DEC(n?1)) according to a comparison result CMP.

Abstract: A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM device (102) and memory device (104) may be connected to one another by point-to-point unidirectional connections. Command data issued by a device, such as a network processing unit (NPU) (110), can flow through all devices beginning with a CAM device (102) and eventually to a memory device (104). A memory device (104) can compare its own current result data with that of a previous device in a flow (such as another RAM device), and generate an output response.

Abstract: A system (100) may include a content addressable memory (CAM) device (102) and at least two requesting devices (104-0 and 104-n). Requesting devices (104-0 and 104-n) and a CAM device (102) may be connected by at least two communication links (106-0 and 106-n). A CAM device (102) may generate responses to requests, and assign a flow identification value for responses based on a communication link (106-0 and 106-n) on which a corresponding request was received.

Abstract: A content addressable memory (CAM) device (100) may include a number of blocks (102-[n?1, n, n+1]) that each generate CAM search results and result compare circuits (104-[n?1, n, n+1] that receive CAM search results from multiple blocks (102-[n?1, n, n?1]), and compare at least a portion of such CAM search results. According to such a comparison result, a compare circuit (104-[n?1, n, n+1]) can generate an output CAM search result for subsequent comparison with CAM search result in another compare circuit (104-[n?1, n, n+1]).