Abstract: A time-to-digital converter obtains a Start signal to indicate the start of an event, and a Stop signal whose assertion indicates the stop of the event. The Stop signal can be asserted multiple times due to false indications of the event stop. The TDC continuously monitors the Stop signal to generate a separate digital value for the duration from the event's starting time to each assertion of the Stop signal. The digital values can be analyzed to select the true duration of the event. Other features and embodiments are also provided.

Abstract: A time-to-digital converter (TDC, 110) obtains a Start signal to indicate the start of an event, and a Stop signal whose assertion indicates the stop of the event. The Stop signal can be asserted multiple times due to false indications of the event stop. The TDC continuously monitors the Stop signal to generate a separate digital value (T.j_i) for the duration from the event's starting time to each assertion of the Stop signal. The digital values can be analyzed to select the true duration of the event. Other features and embodiments are also provided.

Abstract: A hybrid frequency synthesizer includes an analog phase lock loop (PLL), a digital PLL, and a control circuit to control an output oscillator. The control circuit assigns control of the output oscillator between the analog PLL and/or the digital PLL depending on a state of lock of the analog PLL and/or the digital PLL. During a frequency acquisition mode, the digital PLL provides a coarse control of the output oscillator. During a phase capture mode, the analog PLL provides a fine control and the digital PLL provides a coarse control of the output oscillator. During the phase capture mode, the analog PLL control signal and the digital PLL control signal may be given a percentage of control over the output oscillator depending on the state of lock of the analog PLL and/or the digital PLL. During a phase lock mode, the analog PLL controls the output oscillator.

Abstract: A hybrid frequency synthesizer includes an analog phase lock loop (PLL), a PLL, and a control circuit to control an output oscillator. The control circuit combines a control signal from the analog PLL with a control signal from the digital PLL to form a composite control signal. The composite control signal is conditioned depending on a state of lock of the analog PLL and/or the digital PLL. The composite signal controls the phase and frequency of the output oscillator. The analog control signal and the digital PLL control signal may be given a percentage of over the hybrid frequency synthesizer depending on the state of lock of the PLL and/or the digital PLL. The composite control signal provides both rapid, accurate, and robust acquisition by the digital PLL, and a smooth transition thereafter to low noise phase lock by the analog PLL.