Abstract: A planarization process for a double metal very large scale integration (VLSI) technology is disclosed. To compensate for an irregular surface topology encountered in a dielectric medium between the two metals, a CVD dielectric layer and a glass layer are first deposited above the first metal. Then an etch-back process is used to uniformly etch back the CVD dielectric and the glass layers at the same rate, leaving a planarized surface for subsequent deposition of a second dielectric layer and a second metal layer.

Abstract: An Electrically Alterable Read Only Memory device including at least one cell in a substrate having source and drain channels with a memory gate region therebetween with the substrate in the memory gate region having therein a first impurity material of a first conductivity type to establish a desired write threshold voltage and a second impurity material of a second conductivity type opposite to said first type to tailor the surface concentration profiles of the impurity material in the memory gate region of the substrate.

Abstract: An electrically alterable read only memory (EAROM) having a tunneling layer of an insulating material such as silicon dioxide which is grown on the substrate by thermal oxidation carried out at low pressure and a layer of silicon nitride laid down on the tunneling layer by a low-pressure chemical vapor deposition, the interface of the two layers forming a charge storage area with the EAROM having improved read/write switching capability and quality, and improved reliability and memory retentivity characteristics.

Abstract: An electrically alterable read only memory (EAROM) having a tunneling layer of an insulating material such as silicon dioxide which is grown on the substrate by thermal oxidation carried out at low pressure and a layer of silicon nitride laid down on the tunneling layer by a low-pressure chemical vapor deposition, the interface of the two layers forming a charge storage area with the EAROM having improved read/write switching capability and quality, and improved reliability and memory retentivity characteristics.

Abstract: A method for testing a microelectronic circuit to detect process defects which affect first and second characteristics of the circuit elements thereof. The circuit is formed on a semiconductor chip in proximity with an independent test element. The test element is not connected to and does not form a part of the circuit. The circuit elements are tested to detect process defects which affect the first characteristic thereof. The test element is tested to detect process defects which affect the second characteristics of both the circuit elements and the test element. The results of the test on the test element are relied on to determine the acceptability of the second characteristics of the circuit elements. The test on the test element for said second characteristic may be performed at the same time the circuit elements are being tested for said first characteristic.