Abstract: The initial transmission (108) from one subscriber to another subscriber is transmitted at full power. The receiving unit measures the received signal strength and returns a code (118) representing this value in a reply message (114), which is also transmitted at full power. The signal strength of the reply message is determined and may be sent to the replying subscriber unit in a subsequent transmission (122), which may now be accomplished at a reduced power level. Thereafter, both subscribers may modify their respective transmitter power levels during subsequent transmission to minimize battery consumption and maximize the operational life of the subscriber unit.

Abstract: A transceiver must pass through a predetermined area and receive two codes before relocating from a low power to a high power communication system (and vise versa). By determining in which order the two codes were received, the transceiver knows whether it has advanced from a low-to-high or high-to-low power communication system. Accordingly, the transceiver may adjust its transmitter power or other operational parameters to properly operate in both communication system. Also, the transceiver operates to approximate remaining battery life when it determines that it is moving from a low power to a high power mode. In this way, the transceiver may inform an operator of limited operational life in a high power mode, while the individual has an opportunity to obtain additional or a replacement battery.

Abstract: An electronic lock system for a two-way radio. The radio is locked by entering a security code. While locked, the keypad is disabled and cannot be used. In order to unlock the keypad, the proper three-digit code must be entered. If an improper code is entered, the radio automatically transmits a message to indicate the identity of the radio and that an improper code has been entered.

Abstract: An improved communication system is disclosed wherein at least one reprogramming station is added to a communication system. The reprogramming station is constructed and arranged to communicate with the subscriber units thereby either reprogramming or regrouping them. The subscribing units receive the reprogramming command and acknowledge individually, altering a memory means until either reprogrammed back to the original state, or to another state. In another mode, the reprogramming station transmits a regrouping command wherein two or more groups are combined to form a super group.

Abstract: An alphanumeric entry system which is provided with an electronic lock-out feature. The keypad entry system of the present invention comprises an alphanumeric keypad having function keys and display, a microprocessor, and an electronically programmable read-only memory device. The display consists of a series of system related menus as well as an alphanumeric display area. One of the system related menus corresponds to a locking feature, which may be activated by a general purpose function key. In the locking mode, the radio keypad toggles between a locked and unlocked condition as controlled by the function keys in accordance with a predefined sequence. The alphanumeric entry system of the present invention is particularly advantageous for use with portable two-way communications equipment which operate in a plurality of radio systems.

Abstract: An optimized method of bus contention comprising monitoring the bus for an idle or busy bus condition and either attempting an asynchronous bus access if the bus is idle or synchronously attempting a prioritized retry after a busy bus condition is sensed, after a bus access collision is sensed, and upon initial power-up, synchronized to the current message completion. The prioritization comprises a constant time delay plus a bit-time delay proportional to said accessing device's address identification.

Abstract: A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. A battery saving circuit generates a battery saving signal having a predetermined duty cycle and period and is responsive to the phase detector in the synthesizer to disrupt power to the synthesizer while maintaining precise tuning. The battery saver circuit is also responsive to the transceiver. In a normal receive operation, a battery saving circuit synchronizes its battery saving signal with the hold condition of the phase detector to disrupt power to selected modules in the synthesizer without altering the injection frequency of the receiver. In a standby mode, power is disrupted to all modules in the receiver, the selected modules in the phase locked loop and the voltage controlled oscillator.

Abstract: A sample and hold phase detector for a phase locked loop includes a digital detector for detecting the frequency and phase difference between the reference signal and the voltage controlled oscillator (VCO) signal. In a first mode of operation, the digital detector generates a first signal relating the difference in frequency and in a second mode of operation generates a second signal relating the difference in phase. A capacitor stores the first or second signal depending on the operational mode of the digital detector. The capacitor is selectively discharged in response to a discharge signal produced by the digital detector when either the VCO frequency is higher than the reference frequency or following each detection of a phase difference. A first amplifier is used to bypass a portion of the loop filter to effect rapid changes in VCO frequency in the first mode while a second amplifier couples the control voltage to the VCO via the loop filter to maintain proper VCO frequency in the second mode.

Abstract: In a frequency synthesizer phase locked loop including a reference oscillator, a variable reference divider (.div.M), a sample and hold phase detector, a loop filter, a voltage controlled oscillator and a variable divider (.div.N), a voltage converter for controlling the voltage of a control input to the voltage controlled oscillator is disclosed. In the preferred embodiment, the voltage converter has its input connected to the output of a first reference divider in the variable reference divider (.div.M) and its output connected to a control input (varactor diode) of the voltage controlled oscillator. The voltage converter clamps the divider reference signal from the first reference divider and provides a negative voltage level output to bias the varactor diode of the voltage controlled oscillator. Thus, the tuning range of the frequency synthesizer is increased.

Abstract: A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver section and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. The frequency synthesizer includes a multiposition switch which accesses various addressable memory locations in a programmable read-only memory where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. A zone selector switch enables grouping and easy retrievability of channels. The divisors are supplied to a single synchronous binary swallow counter which works in conjunction with a dual modulus prescaler to monitor the frequency output of the voltage controlled oscillator. A programmable divider coupled to a reference oscillator source is compared with the output of the synchronous counter in a digital and analog phase detector.

Abstract: In a transceiver, a synthesizer includes a multiposition switch which accesses various addressable memory locations in a programmable read-only memory (PROM), where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. A zone selector switch enables grouping and easy retrievability of channels. The divisors are supplied to a single synchronous binary swallow counter which works in conjunction with a dual modulus prescaler to monitor the frequency output of the voltage controlled oscillator. In the swallow counting device, two latches receive divisor related information supplied by the PROM. When the sampled state of a single up counter reaches a first latched number, the prescaler changes the modulus. Synchronous counting then continues, without reprogramming new values. When the up counter reaches a second latched number, a predetermined frequency ratio has been achieved, and the counter is reset.

Abstract: A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver section and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. The frequency synthesizer includes a multiposition switch which accesses various addressable memory locations in a programmable read-only memory where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. The multiposition switch has a minimum number of interconnection lines connected to an analysis circuit which identifies the switch position. A zone selector switch enables grouping and easy retrievability of channels. The divisors are supplied to a single synchronous binary swallow counter which works in conjunction with a dual modulus prescaler to monitor the frequency output of the voltage controlled oscillator.

Abstract: A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver section and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. The frequency synthesizer includes a multiposition switch which accesses various addressable memory locations in a programmable read-only memory where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. A zone selector switch enables grouping and easy retrievability of channels. The divisors are supplied to a single synchronous binary swallow counter which works in conjunction with a dual modulus prescaler to monitor the frequency output of the voltage controlled oscillator. A programmable divider coupled to a reference oscillator source is compared with the output of the synchronous counter in a digital and analog phase detector.

Abstract: A frequency synthesized transceiver capable of tuning to a plurality of communication channels is disclosed. The transceiver includes a receiver section and a transmitter section which are coupled to the synthesizer which generates the appropriate injection signals to achieve tuning. The frequency synthesizer includes a multiposition switch which accesses various addressable memory locations in a programmable read-only memory where the appropriate divisors are stored to cause tuning of the synthesizer to the appropriate communication channel. A zone selector switch enables grouping and easy retrievability of channels. The synthesizer includes a priority channel monitoring system utilizing a channel element for rapid sampling. The divisors are supplied to a single synchronous binary swallow counter which works in conjunction with a dual modulus prescaler to monitor the frequency output of the voltage controlled oscillator.