Abstract: A wind turbine including a nacelle and a rotor hub is disclosed. The nacelle may extend between a hub end and an aft end and may define a nacelle shaft opening and a nacelle access port at the hub end. The rotor hub may extend between a first end and a second end, with the second end being disposed adjacent to the hub end of the nacelle. The rotor hub may also define a hub shaft opening at the second end and a hub access port generally adjacent to the hub shaft opening. In addition, the wind turbine may include an access bridge configured to extend between the nacelle and the rotor hub so as to provide access between the nacelle access port and the hub access port.

Abstract: A system and method for lubricating gears in a wind turbine blade pitch drive are provided, wherein the pitch drive comprises a drive pinion gear with gear teeth that engage a pitch bearing gear coupled to a respective wind turbine blade. A grease distributor is configured to mount onto and rotate with the pinion gear, and is configured to deliver grease from an external grease supply to at least one valley defined between adjacent teeth of the pinion gear in a contact area of the pinion gear with the bearing gear without the distributor contacting inter-engaging teeth of the bearing gear.

Abstract: A rotor for a wind turbine is disclosed. The rotor includes a hub, a rotor blade, and a bearing assembly configured to rotate the rotor blade with respect to the hub. The rotor further includes an insert, the insert including a first end, a second end, and a body extending therebetween. The first end is coupled to the bearing assembly and the second end is coupled to the rotor blade. The second end defines a second plane oriented at a cone angle with respect to a first plane defined by the first end.

Abstract: A wind turbine including a nacelle and a rotor hub is disclosed. The nacelle may extend between a hub end and an aft end and may define a nacelle shaft opening and a nacelle access port at the hub end. The rotor hub may extend between a first end and a second end, with the second end being disposed adjacent to the hub end of the nacelle. The rotor hub may also define a hub shaft opening at the second end and a hub access port generally adjacent to the hub shaft opening. In addition, the wind turbine may include an access bridge configured to extend between the nacelle and the rotor hub so as to provide access between the nacelle access port and the hub access port.

Abstract: A system and method for lubricating gears in a wind turbine blade pitch drive are provided, wherein the pitch drive comprises a drive pinion gear with gear teeth that engage a pitch bearing gear coupled to a respective wind turbine blade. A grease distributor is configured to mount onto and rotate with the pinion gear, and is configured to deliver grease from an external grease supply to at least one valley defined between adjacent teeth of the pinion gear in a contact area of the pinion gear with the bearing gear without the distributor contacting inter-engaging teeth of the bearing gear.

Abstract: A rotor blade for a rotor of a wind turbine is provided. The rotor blade comprises a blade root portion configured to transfer a load acting on the rotor blade to the rotor through a blade coupling assembly of the rotor, wherein the blade coupling assembly comprises a rotatable hub and a pitch bearing, and at least one reinforcement element disposed in the blade root portion of the rotor blade for stiffening the blade coupling assembly of the rotor.

Abstract: A data processing system includes a first and a second central system wherein the central processing unit (CPU) of the first central system is operatively connected to the system control unit (SCU) of the second central system and the CPU of the second central system is operatively connected to the SCU of the first central system, each central system including a service processor and a timing subsystem for providing clocking signals. Each central system includes an apparatus for distributing the clocking signals such that each central system is clocked from predetermined ones of the clocking signals in response to control signals from the service processors. The apparatus permits the distribution of the clocking signals to be switched dynamically while the central systems are operating, the switching of the clocking signals being accomplished without affecting the operation of the central systems. The apparatus comprises a generating element for generating local clocking signals.

Abstract: An input/output system includes a plurality of modules and a system interface unit having a plurality of ports, each of which connects to a different one of the modules. The plurality of modules includes at least one processor and one memory module. The system interface unit includes a timer unit and a priority network for processing processor interrupt requests on a priority basis. The priority network connects to a register for storing coded priority level signals to be assigned to the different types of interrupt requests. The register is conditioned to store a low priority level for timer interrupts. The timer unit includes a preset register, an interval counter and a rollover counter. At the completion of each time interval, the interval counter is loaded automatically from the preset register and counting is continued. Simultaneously, the interval counter conditions the rollover counter to store a count registering the total number of completed intervals counted.

Abstract: An input/output system includes a local memory module including a cache store and a backing store. The system includes a plurality of command modules and a system interface unit having a plurality of ports, each connected to a different one of the command modules and to the local memory module. The cache store provides fast access to blocks of information previously fetched from the backing store in response to memory commands generated by any one of a plurality of command modules during both data transfer and data processing operations. The local memory module includes apparatus operative in response to each memory command to enable the command module to write into cache store the data which is requested to be written into backing store when it is established that such data has been previously stored in cache store.

Abstract: An input/output system couples to a host processor through a system interface unit and includes at least two input/output processing units and a memory unit. The system interface unit includes interrupt processing logic circuits for each input/output processing unit for processing interrupt requests on a priority basis. The system interface unit further includes a processor intercommunication network which connects to each of the interrupt processing logic circuits.The input/output operating system initiates an input/output operation in response to a connect interrupt generated by the host processor executing a connect instruction. The interrupt is directed to an assigned input/output processing unit by the System Interface Unit (SIU). The assigned processor executes an instruction sequence which causes an appropriate entry to be placed in an operating system queue located within the memory unit. The queue entry has sufficient data to specify the desired I/O operation.

Abstract: A local memory of an input/output system includes a cache store and a backing store. The system includes a plurality of command modules. The cache store provides fast access to blocks of information previously fetched from the backing store in response to memory commands generated by any one of a plurality of command modules during both data transfer and data processing operations. Each memory command applied to the memory unit incudes a predetermined bit which is coded to designate when the information requested from the local memory unit is to be written into the cache store. The local memory unit includes aparatus operative in response to each memory command to enable the command module to bypass selectively the cache store in accordance with the coding of the predetermined bit thereby enabling the command modules to execute operations more expeditiously during the performance of input/output data transfer operations.

Abstract: An automatic reconfiguration hardware capability for automatically altering the local memory/processor configuration and reinitiating a bootload sequence in the event of a failure in the start-up phase of the input/output processor bootload. The automatic reconfiguration logic is enabled when a bootload request originates from the system console or the central system. Once a bootload request is initiated, all possible local memory/input-output processor (IOPP) configurations are attempted without further manual intervention. If no configuration is successful, a bootload error indication is presented at the I0P configuration panel.

Abstract: Priority interrupt apparatus includes a level priority network, a plurality of priority networks, and selector circuits, each corresponding in number to the number of channel sources operative to generate interrupt requests. Each priority network receives requests signals corresponding to different types of possible event signals requiring attention and produces a type code designating the highest priority event from the channel associated therewith. The priority is established in accordance with a preassigned event priority approximating the priorities assignable by program. Each of the selector circuits is connected to receive as a control input the type code signals generated by the priority network associated therewith. Additionally, each selector circuit receives a different set of interrupt level number signals representative of priorities assigned by program to the number of possible event signals.

Abstract: An input/output processing system includes a plurality of active modules, a plurality of passive modules, at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. The active modules include an input/output processing unit which processes interrupts and executes command signals and at least one multiplexer unit which directly controls transfers between the memory module and any one of a plurality of peripheral devices coupled to different ports of the multiplexer unit. The system interface unit operatively provides connections between different ones of the modules during the execution of commands included within user programs. The multiplexer unit includes sets of registers selectable under program control which store information which enables user programs for accessing the memory module.

Abstract: A firmware/hardware mechanism in a general purpose computer system automatically provides alternate addressing paths for addressing data in the same or another main memory module when a failure is detected in a portion of the main memory or main memory module. Two types of memory failures are detected and an alternate path provided for each type of failure. The first type is a failure in a memory which is not detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an exception processing mechanism to provide an alternate path to a good memory module. The second type of failure is detected by memory hardware or systen interface unit SIU hardware; such failure is handled by an interrupt processing mechanism to provide an alternate path to a good memory module.

Abstract: An input/output data processing system includes a plurality of active modules, a plurality of passive modules and at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. Each module connects to one of the ports by a plurality of different interfaces. The active modules include an input/output processing unit for processing interrupts and executing command sequences and a multiplexer unit for directly controlling transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. Different ones of the modules of the system include the programmable interface used for transferring command information to the multiplexer unit and to the devices associated therewith for enabling a different type of control to proceed in parallel with input/output data transfer operations.

Abstract: High density data storage is permitted on magnetic disk by providing uniform length data sectors and by grouping a plurality of data sectors with a single header. Any data sector may be accessed through location of the desired group header and counting to the position of the sector.

Abstract: Priority interrupt hardware monitors for the existence of, and determines the relative importance of requests to determine or attempt to determine when to interrupt an executing process on a processor. The processor may be interrupted only when the hardware determines that something more important needs to be done than what is being done by the currently executing process. Additionally, the processor may set interrupts for itself so that a portion of an executing process may be executed at a higher priority than that required for the remaining portion of the same process.