Patents by Inventor Jaime Poris

Jaime Poris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8825444
    Abstract: A metrology unit includes an integrated reference target with which an automated system check process is performed. The automated system check process includes measuring a feature on the reference target and determining if the measurement is within a desired specification for the metrology unit. When the metrology unit fails the automated system check, or if otherwise warranted, an automated diagnosis process may be performed using the same integrated reference target. The automated system check and automated diagnosis may be optimized based on correlations between parameters of the automated qualification and parameters of the automated diagnosis. Similarly, the measurement of a processed wafer may be optimized based on a correlation between parameters of the metrology of the processed wafer and parameters of the automated system check.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: September 2, 2014
    Assignee: Nanometrics Incorporated
    Inventors: Pablo I. Rovira, Jaime Poris, Jonathan M. Madsen, Scott D. Penner
  • Publication number: 20090148256
    Abstract: A chuck, which may hold a substrate during stress measurements, includes a number of pins that support the substrate. Each support pin has a dome shaped upper surface that contacts a bottom surface of a substrate when supporting the substrate. The dome shaped upper surface minimizes contact with the substrate as well as assists in maintaining the same contact location with the substrate regardless of substrate shape. The dome shaped upper surface may be formed of a layer of soft material having a high coefficient of static friction to hold the substrate stationary with respect to the pins when the chuck is accelerated moved during or between stress measurements. Additionally, the layer of soft material may be a thin layer that covers a hard internal dome to reduce creep.
    Type: Application
    Filed: December 10, 2007
    Publication date: June 11, 2009
    Applicant: Nanometrics Incorporated
    Inventor: Jaime Poris
  • Patent number: 7173417
    Abstract: A metrology instrument includes an eddy current sensor that is mounted to and concentric with a confocal distance sensor. By measuring the precise vertical placement of the eddy current probe with respect to the surface of the sample using the confocal distance sensor, the accuracy and precision of the eddy current measurement is improved. Because the confocal distance sensor and the eddy current sensor are confocal, there is no need to move the relative lateral positions between the sample and instrument, between the distance measurement and the eddy current measurement, thereby reducing error in the measurement as well are maximizing the throughput by minimizing the required stage travel for a single measurement.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: February 6, 2007
    Assignee: Nanometrics Incorporated
    Inventors: Jaime Poris, Claudio L. Rampoldi, Pablo I. Rovira, Christopher W. Blaufus
  • Patent number: 7061613
    Abstract: An ellipsometer with a variable retarder, which introduces a spatial dependence in the beam, includes a polarizing beam splitter to produce two beams with orthogonal polarization states. The beam splitter may be, e.g., a polarizing displacer or polarizing beam splitter. The intensities of the two beams are measured, e.g., using separate detectors or separate detector elements in an array. The intensity from the two beams may be summed and used as a reference to normalize intensity of the produced beam.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: June 13, 2006
    Assignee: Nanometrics Incorporated
    Inventors: Chunsheng Huang, Pablo I. Rovira, Jaime Poris
  • Patent number: 7005306
    Abstract: The thickness of a thin conductive film is accurately measured without direct knowledge of the temperature of the sample. A coulometer measurement during deposition of the conductive film on a substrate, along with other data such as the plated surface area, the electrochemical reaction, the molar volume of the deposited metal and the coulombic efficiency, is used to determine the average thickness of the film. Eddy current measurements yield the sheet resistance of the film at a plurality of locations, from which the average sheet resistance can be determined. The eddy current measurements are made so as to reduce the effects of any temperature change in the sample. The average thickness and the average sheet resistance yield the average resistivity of the film. The thickness of the film at a measurement location can be calculated using that average resistivity and the sheet resistance measurement at that location.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: February 28, 2006
    Assignee: Nanometrics Incorporated
    Inventor: Jaime Poris
  • Patent number: 6925860
    Abstract: The height profile of a sample that includes at least one film on a substrate is leveled based on the measured thickness of the overlying film. An apparatus that levels the height profile includes a metrology tool that generates the height profile of a sample and a metrology tool that measures the thickness of one or more layers of a film stack on top of a substrate at two or more locations. The measured thickness is then used to level the height profile to reduce any tilt error before a step height calculation is made. For example, the slope of the thickness between two or more measurement points may be used to adjust the height profile. Once the height profile is leveled, step heights may be calculated with reduced tilting error.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: August 9, 2005
    Assignee: Nanometrics Incorporated
    Inventors: Jaime Poris, Claudio L. Rampoldi
  • Patent number: 6853873
    Abstract: The throughput of a metrology module is enhanced by measuring a first parameter of a processed substrate and only measuring additional parameters if warranted from an analysis of the first parameter. Thus, after a substrate is processed, a first parameter related to the processing is measured and analyzed. If the measured parameter falls within accepted tolerance, the data is reported and then next substrate is processed. If, however, the measured parameter falls outside the range of accepted tolerance, the second parameter or additional parameters are measured and analyzed. The data can then be reported, the processing of subsequent substrate stopped and/or the processing of subsequent substrates adjusted based on the analyzed data.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: February 8, 2005
    Assignee: Nanometrics Incorporated
    Inventors: Jason H. Rollo, Jaime Poris
  • Patent number: 6813031
    Abstract: A profiling method compensates for phase changes associated with the presence of multiple or varying material in the area to be measured. The profiling method measures at least a portion of the height profile of the area of interest. The phase of the different materials in the region are also obtained and used to generate a correction factor. Depending on the type of material in the region of interest, the correction factor may be the material specific phase difference of the materials in the region, e g., when at least one of the materials is opaque to the wavelength of light used to measure the height profile, or the relationship between the thickness and phase of the material for a desired thickness range, e.g., when one or more of the materials is transparent to the wavelengths used to measure the height profile. The correction factor is then used to correct and/or convert the measured phase profile to an actual height profile.
    Type: Grant
    Filed: August 4, 2003
    Date of Patent: November 2, 2004
    Assignee: Nanometrics Incorporated
    Inventors: Jaime Poris, Claudio L. Rampoldi
  • Patent number: 6772620
    Abstract: A metrology process, in accordance with the present invention, measures the dishing of a first feature made of a first material by determining the relative height of the first feature with respect to a second feature, where the first and second features have different dishing rates. The relative height of the first feature with respect to the second feature may be determined by measuring a first relative height of the first feature with respect to a reference location, measuring a second relative height of the second feature with respect to a reference location, and calculating the difference between the first and second relative heights. Alternatively, other methods may be used. The relative height is then correlated with calibration data to determine the amount of dishing of the first feature. The calibration data is generated by first providing a sample substrate with features approximately the same as the substrate to be measured, e.g.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: August 10, 2004
    Assignee: Nanometrics Incorporated
    Inventor: Jaime Poris
  • Patent number: 6762846
    Abstract: The focusing capability of a metrology tool is used to determine the surface profile of a substrate and the stress on the substrate that is associated with processing step, such as layer deposition or etching. The amount of focusing adjustment necessary to place the substrate in focus is used to determine the height of the surface of the substrate at three or more locations. Based on the surface profile, a curvature parameter may be calculated. The curvature parameter may be calculated before and after a processing step. The stress associated with the processing step can then determined from these two curvature parameters.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: July 13, 2004
    Assignee: Nanometrics Incorporated
    Inventor: Jaime Poris
  • Patent number: 6710888
    Abstract: A metrology process, in accordance with the present invention, measures the dishing of an opaque feature with respect to a relatively transparent feature that surrounds the opaque feature on a production substrate by measuring only height variation of the opaque feature. The opaque feature may be, for example, a metal or metal alloy line containing, e.g., copper, aluminum, or tungsten, while the relatively transparent feature is a dielectric material. The metrology process is useful, for example, after the metal and dielectric materials undergo a polishing process, e.g., CMP, to approximately planarize the surface. The method includes generating a set of calibration data or curves that correlate the magnitude of dishing with the width of a metal line and the profile, shape, or height variation of the metal line. In addition, different sets of calibration data may be generated based on different parameters used in the polishing process. The height variation of the metal line is measured using, e.g.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: March 23, 2004
    Assignee: Nanometrics Incorporated
    Inventor: Jaime Poris
  • Patent number: 6700670
    Abstract: A metrology process, in accordance with the present invention, measures the dishing of a feature, such as a copper, aluminum, or tungsten metal line, with respect to another feature, such as a dielectric layer, that surround the first feature by measuring the relative heights of varying line widths of the first feature with respect to the second feature. The relative heights are adjusted to correspond to the actual dishing value using a calibration point of a calibration line width and a calibration dishing value. The metrology process is useful, for example, after the metal and dielectric materials undergo a polishing process, e.g., CMP, to approximately planarize the surface. The calibration data provides a dishing value at a specific, relatively, small line width. The relative heights of various line widths are measured on production substrates. These relative heights are plotted as a function of line width. The curve is then extrapolated to the line width used during calibration.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: March 2, 2004
    Assignee: Nanometrics Incorporated
    Inventor: Jaime Poris
  • Patent number: 6657216
    Abstract: A confocal displacement sensor uses one or two light sources and produces two spots on a sample surface. The reflected intensities from the two spots are detected and measured by one or two detectors. A vertical resolution enhancement can be implemented by modifying the properties of the objective and/or detector lenses. The resultant height profile does not need to be corrected for tilt as is common with all single point surface measurement techniques. A differential scan can be performed with the two spots relatively close together to generate the slope of the height profile. Integrating this profile yields the height profile of the scan. A referential scan can be performed by scanning the reference point across an area of constant height and the measurement point scanned across the feature to be measured to directly generate the height profile.
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: December 2, 2003
    Assignee: Nanometrics Incorporated
    Inventor: Jaime Poris
  • Patent number: 6633389
    Abstract: A profiling method compensates for phase changes associated with the presence of multiple or varying material in the area to be measured. The profiling method measures at least a portion of the height profile of the area of interest. The phase of the different materials in the region are also obtained and used to generate a correction factor. Depending on the type of material in the region of interest, the correction factor may be the material specific phase difference of the materials in the region, e.g., when at least one of the materials is opaque to the wavelength of light used to measure the height profile, or the relationship between the thickness and phase of the material for a desired thickness range, e.g., when one or more of the materials is transparent to the wavelengths used to measure the height profile. The correction factor is then used to correct and/or convert the measured phase profile to an actual height profile.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: October 14, 2003
    Assignee: Nanometrics Incorporated
    Inventors: Jaime Poris, Claudio L. Rampoldi
  • Patent number: 6568290
    Abstract: A metrology process, in accordance with the present invention, measures the dishing of a first feature made of a first material by determining the relative height of the first feature with respect to a second feature, where the first and second features have different dishing rates. The relative height of the first feature with respect to the second feature may be determined by measuring a first relative height of the first feature with respect to a reference location, measuring a second relative height of the second feature with respect to a reference location, and calculating the difference between the first and second relative heights. Alternatively, other methods may be used. The relative height is then correlated with calibration data to determine the amount of dishing of the first feature. The calibration data is generated by first providing a sample substrate with features approximately the same as the substrate to be measured, e.g.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: May 27, 2003
    Assignee: Nanometrics Incorporated
    Inventor: Jaime Poris
  • Patent number: 5723028
    Abstract: An electrochemical etching step in a semiconductor device fabrication process increases the radius of curvature of edges of metal lines deposited on the semiconductor device. The metal lines are fabricated by forming a mask, electrodepositing the metal, and removing the mask, and the electrochemical etching step in performed subsequently. The increased radius of curvature of the metal lines simplifies subsequent planarization and decreases line-to-line capacitance, thereby enhancing device performance. In an apparatus for performing the fabrication process, wires sown into a gasket which secures the semiconductor wafer and prevents electrolyte leakage, allows the gasket to function also as a component of the cathode. A more uniform metal deposition is created by a virtual anode, i.e., a metal plate having an aperture and being located between the anode and the cathode.
    Type: Grant
    Filed: October 19, 1994
    Date of Patent: March 3, 1998
    Inventor: Jaime Poris
  • Patent number: 5625170
    Abstract: A time delayed differential weighing procedure used with an electronic analytical balance is optimized for samples exhibiting a small change in mass, for example from deposition, etching, plating or corroding, relative to the sample mass to minimize all significant sources of error that could otherwise degrade the measurement results, such as errors resulting from air density and temperature changes that occur during the interval between the first measurement of a sample, before the sample is processed, and a subsequent measurement of the sample, after the sample is processed. A calibration standard having substantially the same density as that of the sample is weighed both times the sample is weighed, i.e. before and after processing, to track the change in the sample balance reading due to air density and temperature changes, and thereby eliminate sample related errors. Balance and weighing procedure accuracy and precision are tested by a gauge study procedure.
    Type: Grant
    Filed: January 18, 1994
    Date of Patent: April 29, 1997
    Assignee: Nanometrics Incorporated
    Inventor: Jaime Poris
  • Patent number: 5368711
    Abstract: A process and apparatus for advanced semiconductor applications which involves the selective electrodeposition of metal on a semiconductor wafer is described. The present invention has significant economic and performance advantages over the current state of the art. It addresses problems associated with cleanliness (a major issue with sub-micron processing), metal thickness uniformity, step coverage and environmental concerns.A metal with better device performance capabilities compared to the standard aluminum is also employed. The hardware allows the selective deposition to occur without allowing the electrolyte to contact the rear of the wafer or the electrodes contacting the front wafer surface. A virtual anode improves the primary current distribution improving the thickness uniformity while allowing optimization of other film parameters with the remaining deposition variables.
    Type: Grant
    Filed: April 29, 1993
    Date of Patent: November 29, 1994
    Inventor: Jaime Poris
  • Patent number: 5256274
    Abstract: A process and apparatus for advanced semiconductor applications which involves the selective electrodeposition of metal on a semiconductor wafer is described. The present invention has significant economic and performance advantages over the current state of the art. It addresses problems associated with cleanliness (a major issue with sub-micron processing) , metal thickness uniformity, step coverage and environmental concerns.A metal with better device performance capabilities compared to the standard aluminum is also employed. The hardware allows the selective deposition to occur without allowing the electrolyte to contact the rear of the wafer or the electrodes contacting the front wafer surface. A virtual anode improves the primary current distribution improving the thickness uniformity while allowing optimization of other film parameters with the remaining deposition variables.
    Type: Grant
    Filed: November 22, 1991
    Date of Patent: October 26, 1993
    Inventor: Jaime Poris
  • Patent number: RE37749
    Abstract: An electrochemical etching step in a semiconductor device fabrication process increases the radius of curvature of edges of metal lines deposited on the semiconductor device. The metal lines are fabricated by forming a mask, electrodepositing the metal, and removing the mask, and the electro-chemical etching step in performed subsequently. The increased radius of curvature of the metal lines simplifies subsequent planarization and decreases line-to-line capacitance, thereby enhancing device performance. In an apparatus for performing the fabrication process, wires sown into a gasket which secures the semiconductor wafer and prevents electrolyte leakage, allows the gasket to function also as a component of the cathode. A more uniform metal deposition is created by a virtual anode, i.e., a metal plate having an aperture and being located between the anode and the cathode.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: June 18, 2002
    Inventor: Jaime Poris