Abstract: A clock dividing frequency circuit can include: a controlled current source configured to generate a driving current that varies with a dividing frequency control signal; a ramp signal generating circuit configured to generate a ramp signal having a slope that varies according to the driving current, where the ramp signal is reset according to pulses of a dividing frequency clock signal; and a dividing frequency pulse generating circuit configured to generate the dividing frequency clock signal by a dividing frequency operation according to the ramp signal and a system clock signal.

Abstract: A clock dividing frequency circuit can include: a controlled current source configured to generate a driving current that varies with a dividing frequency control signal; a ramp signal generating circuit configured to generate a ramp signal having a slope that varies according to the driving current, where the ramp signal is reset according to pulses of a dividing frequency clock signal; and a dividing frequency pulse generating circuit configured to generate the dividing frequency clock signal by a dividing frequency operation according to the ramp signal and a system clock signal.

Abstract: Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current.

Abstract: Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current.

Abstract: Methods and circuits related to a driving circuit with zero current shutdown are disclosed. In one embodiment, a driving circuit with zero current shutdown can include: a linear regulating circuit that receives an input voltage source, and outputs an output voltage; a start-up circuit having a threshold voltage, the start-up circuit receiving an external enable signal; a first power switch receiving both the output voltage of the linear regulating circuit and the external enable signal, and that generates an internal enable signal, the internal enable signal being configured to drive a logic circuit; when the external enable signal is lower than a threshold voltage, the driving circuit is not effective; when the external enable signal is higher than the threshold voltage, the start-up circuit outputs a first current; and where the output voltage at the first output terminal is generated by the linear regulating circuit based on the first current.

Abstract: An oscillator that includes an energy storage system configured to store energy, a ramp circuit configured to generate an oscillating ramp signal having a slope that is a function of the amount of energy stored in the energy storage system, a charge circuit configured to controllably deliver energy into or remove energy from the energy storage system, a comparator circuit configured to compare the oscillating ramp signal with a reference signal; and/or a charge control circuit configured to cause the charge circuit to deliver energy into or remove energy from the energy storage system based on the comparison by the comparator circuit.

Abstract: An adaptive current reversal comparator for synchronous switching regulator comparison circuit for use in a switching regulator is provided. The comparison circuit includes a voltage offset that is used at least in part to compensate for a propagation delay of the comparison circuit. The switching regulator includes an inductor and a synchronous transistor. The comparison circuit also includes a timing circuit that provides a threshold amount of time and an offset adjustment circuit. The offset adjustment circuit preferably decreases the voltage offset of the comparison circuit when a synchronous transistor control signal transitions to an OFF state more than the threshold amount of time prior to the discharge of an inductor. The comparison circuit also increases the voltage offset of the comparison circuit when the synchronous control signal transitions to an OFF state more than the threshold amount of time following the discharge of the inductor.

Abstract: An adaptive current reversal comparator for synchronous switching regulator comparison circuit for use in a switching regulator is provided. The comparison circuit includes a voltage offset that is used at least in part to compensate for a propagation delay of the comparison circuit. The switching regulator includes an inductor and a synchronous transistor. The comparison circuit also includes a timing circuit that provides a threshold amount of time and an offset adjustment circuit. The offset adjustment circuit preferably decreases the voltage offset of the comparison circuit when a synchronous transistor control signal transitions to an OFF state more than the threshold amount of time prior to the discharge of an inductor. The comparison circuit also increases the voltage offset of the comparison circuit when the synchronous control signal transitions to an OFF state more than the threshold amount of time following the discharge of the inductor.