Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.

Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.

Abstract: A system may include a digitally-controlled oscillator configured to generate an output clock signal based on a control signal received at an input of the digitally-controlled oscillator and a control circuit configured to calculate an error signal between the output clock signal and an external reference clock signal, filter the error signal to generate a correction signal, generate the control signal based on the correction signal, and switch between a first mode of operation and a second mode of operation without artifacts on the correction signal during switching between the first mode and the second mode.

Abstract: A method and apparatus for detecting a microphone condition of a microphone, the method comprising: applying an electrical stimulus to a microphone; measuring an electrical response to the electrical stimulus at the microphone; comparing the electrical response to an expected response; and determining the microphone condition based on the comparison.

Abstract: A system and method of regularizing data between a data source and a data destination, wherein the given data category includes with specific data fields. The system includes a data processing arrangement that includes a data fetching module operable to fetch data from the data source. Furthermore, the data processing arrangement includes a data transformation module that is operable to receive pre-defined data formats for a specific data category, compare data formats of the fetched data with pre-defined data formats, determine a deviation therein, and thereafter transform the data format. Additionally, the data processing arrangement includes a data validation module operable that is to receive the transformed data or the fetched data, confirm if data formats of a received data are same as corresponding pre-defined data formats, identify from the received data regularized data, and transmit the regularized data to the data destination implemented as database arrangement.

Abstract: A system and method for managing clinical trials data. The system includes a database arrangement operable to store existing data sources and aggregated clinical trial; and a processing module communicably coupled to the database arrangement. The processing module operable to identify a set of clinical trials; extract clinical trials data from existing data sources; classify the clinical trial entries into one or more predefined classes; compare the clinical trial entries in each of the one or more predefined classes, to identify similarity or dissimilarity between the clinical trial entries in a predefined class; compile the first and second aggregated clinical trial entries to obtain class-specific clinical trial entries corresponding to each of the one or more predefined classes; and collate class-specific clinical trial entries corresponding to each of the one or more predefined classes to obtain an aggregated clinical trial.

Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.

Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.

Abstract: Aperiodic clock generation with clock spur suppression is based on cascaded randomizers, such as for mixed signal devices. A clock generator circuit includes an input node to receive the input periodic clock signal having an input-clock frequency. A first randomizer circuit coupled to receive the input clock signal from the input node, to perform signal randomization to suppress spurious signal content associated with (a) the input clock signal, and (b) the first randomizer circuit, and to generate an intermediate clock signal. A second concatenated randomizer circuit is coupled to receive the intermediate clock signal, to perform signal randomization to suppress spurious signal content associated with (a) the intermediated clock signal, and (b) the second randomizer circuit, and to generate an aperiodic output clock signal having a pre-defined average output-clock frequency that is less than the input-clock frequency. Example randomizers are a delta-sigma divider and a pulse swallower (in any order).

Abstract: A system may include control circuitry for detecting a plosive event associated with a microphone transducer and in response to the plosive event, causing restoration of acoustic sense operation of the microphone transducer and a processing circuit associated with the microphone transducer. A system for configuring a filter having at least two frequency response configurations to achieve an effective frequency response configuration intermediate to the at least two frequency response configurations may include control circuitry for rapidly switching between the at least two frequency response configurations such that a weighted average frequency response of the filter corresponds to the effective frequency response configuration.

Abstract: A system may include a sampling circuit, a temperature calibration system, a phase detector, a virtual phase-locked loop, and a sample rate converter. The sampling circuit may be configured to generate a series of digitally-sampled data at a sampling frequency provided by a local clock. The temperature calibration system may be configured to determine a temperature-based timing compensation with respect to the local clock. The phase detector may be configured to estimate an error of the local clock in view of the reference clock. The virtual phase-locked loop may be configured to generate a virtual clock based on the temperature-based timing compensation and the error. The sample rate converter may be configured to generate a corrected series of digitally-sampled data in response to the virtual clock by interpolating the series of digitally-sampled data to correct for the error.

Abstract: A system may include control circuitry for detecting a plosive event associated with a microphone transducer and in response to the plosive event, causing restoration of acoustic sense operation of the microphone transducer and a processing circuit associated with the microphone transducer. A system for configuring a filter having at least two frequency response configurations to achieve an effective frequency response configuration intermediate to the at least two frequency response configurations may include control circuitry for rapidly switching between the at least two frequency response configurations such that a weighted average frequency response of the filter corresponds to the effective frequency response configuration.

Abstract: A system may include control circuitry for detecting a plosive event associated with a microphone transducer and in response to the plosive event, causing restoration of acoustic sense operation of the microphone transducer and a processing circuit associated with the microphone transducer. A system for configuring a filter having at least two frequency response configurations to achieve an effective frequency response configuration intermediate to the at least two frequency response configurations may include control circuitry for rapidly switching between the at least two frequency response configurations such that a weighted average frequency response of the filter corresponds to the effective frequency response configuration.

Abstract: A system may include control circuitry for detecting a plosive event associated with a microphone transducer and in response to the plosive event, causing restoration of acoustic sense operation of the microphone transducer and a processing circuit associated with the microphone transducer. A system for configuring a filter having at least two frequency response configurations to achieve an effective frequency response configuration intermediate to the at least two frequency response configurations may include control circuitry for rapidly switching between the at least two frequency response configurations such that a weighted average frequency response of the filter corresponds to the effective frequency response configuration.

Abstract: An apparatus may include a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having a plurality of possible quantization values. The scrambler element may generate at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value. For each of one or more of the possible quantization values, the scrambler element may be configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal. Responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element may change the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal.

Abstract: An apparatus may include a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having a plurality of possible quantization values. The scrambler element may generate at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value. For each of one or more of the possible quantization values, the scrambler element may be configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal. Responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element may change the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal.

Abstract: A system may include a sampling circuit, a temperature calibration system, a phase detector, a virtual phase-locked loop, and a sample rate converter. The sampling circuit may be configured to generate a series of digitally-sampled data at a sampling frequency provided by a local clock. The temperature calibration system may be configured to determine a temperature-based timing compensation with respect to the local clock. The phase detector may be configured to estimate an error of the local clock in view of the reference clock. The virtual phase-locked loop may be configured to generate a virtual clock based on the temperature-based timing compensation and the error. The sample rate converter may be configured to generate a corrected series of digitally-sampled data in response to the virtual clock by interpolating the series of digitally-sampled data to correct for the error.

Abstract: A system comprising a pre-power amplifier and a hardware device which is configured to predistort an amplitude input signal by comparing interpolated data places, determined by comparing the input signal with data from a LUT, coming from a LUT with the amplitude input signal and choosing the closest input data place to the amplitude input signal to produce an amplitude predistortion output signal. The LUT contains predistortion data associated with the pre-power amplifier. The amplitude input signal is multiplied and scaled prior to being compared with the data in the LUT. A second LUT is used to predistort a phase input signal and the phase predistortion output signal is combined in the pre-power amplifier with the amplitude predistortion output signal. The system may be implemented in a mobile communications device.

Abstract: Predistortion methods and apparatus for transmitter linearization in a communication transceiver are disclosed.

Abstract: A novel and useful apparatus for and method of predistortion compensation of device (e.g., transistor) mismatch in a digital power amplifier (DPA). The device mismatch predistortion mechanism of the present invention addresses the problem of matching between two types of binary weighted transistors, whereby mismatched transistors cause degradation in wideband noise. The invention provides a digital predistortion mechanism which functions to pre-distort the mismatch ratio based on a data table calculated a priori enabling a polar transmitter to meet output spectrum and error vector magnitude (EVM) requirements of the particular modern wideband wireless standard, such as GSM, 3G WCDMA, etc.