Abstract: An output buffer precharge circuit for DRAM (dynamic random access memory) cells includes a latch, control circuits, an output buffer, and a precharge pulse generating section. The circuit further includes a data transition signal genrating section consisting of MOS (metal-oxide semiconductor) transistors, latches connected to the MOS transistors, inverters and NAND gates for receiving the control precharge pulse from the precharge pulse generating section; and a precharge section consisting of MOS transistors, the gates of which receive the outputs of the data transition signal generating section. Noise can be decreased during the transition from the CMOS level to the TTL (transistor-transition-logic) level, and valid data are charged or discharged in advance so that processing speed can be increased.

Abstract: The row address strobe signal input buffer, or "chain pre-charge" circuit, includes a pad receiving a row address strobe signal (RAS). A Schmitt trigger receives the RAS signal from the pad, and is responsive to a start-up signal. A control section responds to the start-up signal and the output thereof is connected to the output of the Schmitt trigger. A NAND gate and inverters are connected to the output of the control section. A first pre-charge circuit, connected between the pad and the Schmitt trigger, prevents a floating state at the time of initial power source voltage supply. A second pre-charge circuit, connected to an input of one of the inverters which provides the output of the row address strobe signal input buffer, also helps prevent the floating state.