Abstract: A circuit generally having a first module, a second module and a third module is disclosed. The first module may be configured to (i) generate a plurality of parsed residual blocks by parsing an 8×8 CABAC (context-based adaptive binary arithmetic coding) residual block received in an input signal and (ii) generate a plurality of metric signals resulting from the parsing of the 8×8 CABAC residual block. The second module may be configured to generate a scanning position signal based on the metric signals. The third module may be configured to generating a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks in an output signal by sub-sampling the parsed residual blocks based on the scanning position signal.

Abstract: A circuit generally having a first module, a second module and a third module is disclosed. The first module may be configured to (i) generate a plurality of parsed residual blocks by parsing an 8×8 CABAC (context-based adaptive binary arithmetic coding) residual block received in an input signal and (ii) generate a plurality of metric signals resulting from the parsing of the 8×8 CABAC residual block. The second module may be configured to generate a scanning position signal based on the metric signals. The third module may be configured to generating a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks in an output signal by sub-sampling the parsed residual blocks based on the scanning position signal.

Abstract: A circuit generally including a first module, a second module and a third module is disclosed. The first module may be configured to (i) generate a plurality of parsed residual blocks by parsing a plurality of 4×4 CAVLC (context-based adaptive variable length coding) residual blocks received in an input signal and (ii) generate a plurality of metric signals resulting from the parsing of the 4×4 CAVLC residual blocks. The second module configured to generate a plurality of scanning position signals based on the metric signals. The third module configured to generating an 8×8 CABAC (context-based adaptive binary arithmetic coding) residual block in an output signal by up-sampling the parsed residual blocks based on the scanning position signals.

Abstract: A delay locked loop based clocking circuit includes a lead delay line followed by a period delay line. The lead delay line receives an input clock signal and includes an analog delay control input. The period delay line has a plurality of taps and an analog delay control input, and is operated such that the N taps divide a single period of an input clock. A selected tap of the period delay line, sometimes called a “virtual zero-degree tap,” is fed back and phase-compared with the input clock signal to adjust the delay of the lead delay line.