Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.

Abstract: A chemical-mechanical polishing system includes a rotatable head for mounting a wafer thereto, a polishing pad mounted to a rotatable platen, and a fluid dispenser for dispensing a fluid onto a surface of the polishing pad. The polishing pad includes an array of piezoelectric actuators. The chemical-mechanical polishing system includes a controller operably coupled to each piezoelectric actuator. The controller measures voltages output by the piezoelectric actuators of the array, determines, qualitatively, a topography of the wafer surface based on the measured voltages, and adjusts an aggressiveness of at least one portion of the polishing pad based on the determined topography. The controller adjusts the aggressiveness by inducing the piezoelectric effect or reverse piezoelectric effect in one or more piezoelectric actuators to adjust a surface topography of the polishing pad.

Abstract: Semiconductor devices with on-pitch vias, and associated systems and methods, are disclosed herein. In one embodiment, the semiconductor device may include a 3-dimensional (3D) cross-point memory array. The semiconductor device also includes access lines for the memory array, which couple with on-pitch vias connected to CMOS circuitry disposed underneath the memory array. In some embodiments, a first access line may be coupled with a first via outside a boundary of the memory array, where the first via is separated from the boundary by a first distance and has a first length longitudinal to the first access line. Further, a second access line may be coupled with a second via outside the boundary, where the second via is separated from the boundary by a second distance greater than the first distance and has a second length longitudinal to the second access line, the second length different from the first length.

Abstract: Semiconductor devices with on-pitch vias, and associated systems and methods, are disclosed herein. In one embodiment, the semiconductor device may include a 3-dimensional (3D) cross-point memory array. The semiconductor device also includes access lines for the memory array, which couple with on-pitch vias connected to CMOS circuitry disposed underneath the memory array. In some embodiments, a first access line may be coupled with a first via outside a boundary of the memory array, where the first via is separated from the boundary by a first distance and has a first length longitudinal to the first access line. Further, a second access line may be coupled with a second via outside the boundary, where the second via is separated from the boundary by a second distance greater than the first distance and has a second length longitudinal to the second access line, the second length different from the first length.

Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.

Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.

Abstract: A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.

Abstract: Semiconductor devices with on-pitch vias, and associated systems and methods, are disclosed herein. In one embodiment, the semiconductor device may include a 3-dimensional (3D) cross-point memory array. The semiconductor device also includes access lines for the memory array, which couple with on-pitch vias connected to CMOS circuitry disposed underneath the memory array. In some embodiments, a first access line may be coupled with a first via outside a boundary of the memory array, where the first via is separated from the boundary by a first distance and has a first length longitudinal to the first access line. Further, a second access line may be coupled with a second via outside the boundary, where the second via is separated from the boundary by a second distance greater than the first distance and has a second length longitudinal to the second access line, the second length different from the first length.

Abstract: A chemical-mechanical polishing system includes a rotatable head for mounting a wafer thereto, a polishing pad mounted to a rotatable platen, and a fluid dispenser for dispensing a fluid onto a surface of the polishing pad. The polishing pad includes an array of piezoelectric actuators. The chemical-mechanical polishing system include a controller operably coupled to each piezoelectric actuator. The controller measures voltages output by the piezoelectric actuators of the array, determines, qualitatively, a topography of the wafer surface based on the measured voltages, and adjusts an aggressiveness of at least one portion of the polishing pad based on the determined topography. The controller adjusts the aggressiveness by inducing the piezoelectric effect or reverse piezoelectric effect in one or more piezoelectric actuators to adjust a surface topography of the polishing pad.

Abstract: A semiconductor device includes memory cells, a first dielectric liner material overlying side surfaces of the memory cells, a high-k dielectric material overlying side surfaces of the first dielectric liner material, a second dielectric liner material overlying side surfaces of the high-k dielectric material, and an additional dielectric material overlying side surfaces of the second dielectric liner material. A memory structure, an electronic system, and a method of forming a memory structure are also described.

Abstract: Some embodiments include an apparatus having a polishing mechanism configured to polish a surface of a wafer. The polishing mechanism converts fresh slurry to used slurry during a polishing process. At least one emitter is configured to direct electromagnetic radiation onto or through the used slurry. At least one detector is configured to detect transmittance of the electromagnetic radiation through the used slurry or reflection of the electromagnetic radiation from the used slurry. An identification system is coupled with the at least one detector and is configured to identify a property of the used slurry indicating that an endpoint of the polishing process has been reached. Control circuitry is coupled with the identification system and is configured to stop the polishing process based on receiving a trigger from the identification system. Some embodiments include polishing methods.

Abstract: Some embodiments include an apparatus having a polishing mechanism configured to polish a surface of a wafer. The polishing mechanism converts fresh slurry to used slurry during a polishing process. At least one emitter is configured to direct electromagnetic radiation onto or through the used slurry. At least one detector is configured to detect transmittance of the electromagnetic radiation through the used slurry or reflection of the electromagnetic radiation from the used slurry. An identification system is coupled with the at least one detector and is configured to identify a property of the used slurry indicating that an endpoint of the polishing process has been reached. Control circuitry is coupled with the identification system and is configured to stop the polishing process based on receiving a trigger from the identification system. Some embodiments include polishing methods.

Abstract: A semiconductor device includes memory cells, a first dielectric liner material overlying side surfaces of the memory cells, a high-k dielectric material overlying side surfaces of the first dielectric liner material, a second dielectric liner material overlying side surfaces of the high-k dielectric material, and an additional dielectric material overlying side surfaces of the second dielectric liner material. A memory structure, an electronic system, and a method of forming a memory structure are also described.

Abstract: Some embodiments include an apparatus having a polishing mechanism configured to polish a surface of a wafer. The polishing mechanism converts fresh slurry to used slurry during a polishing process. At least one emitter is configured to direct electromagnetic radiation onto or through the used slurry. At least one detector is configured to detect transmittance of the electromagnetic radiation through the used slurry or reflection of the electromagnetic radiation from the used slurry. An identification system is coupled with the at least one detector and is configured to identify a property of the used slurry indicating that an endpoint of the polishing process has been reached. Control circuitry is coupled with the identification system and is configured to stop the polishing process based on receiving a trigger from the identification system. Some embodiments include polishing methods.

Abstract: Some embodiments include an apparatus having a polishing mechanism configured to polish a surface of a wafer. The polishing mechanism converts fresh slurry to used slurry during a polishing process. At least one emitter is configured to direct electromagnetic radiation onto or through the used slurry. At least one detector is configured to detect transmittance of the electromagnetic radiation through the used slurry or reflection of the electromagnetic radiation from the used slurry. An identification system is coupled with the at least one detector and is configured to identify a property of the used slurry indicating that an endpoint of the polishing process has been reached. Control circuitry is coupled with the identification system and is configured to stop the polishing process based on receiving a trigger from the identification system. Some embodiments include polishing methods.

Abstract: A semiconductor device comprises includes memory cells, a first dielectric liner material overlying side surfaces of the memory cells, a high-k dielectric material overlying side surfaces of the first dielectric liner material, a second dielectric liner material overlying side surfaces of the high-k dielectric material, and an additional dielectric material overlying side surfaces of the second dielectric liner material. A memory structure, an electronic system, and a method of forming a memory structure are also described.