Patents by Inventor James A. Fuxa
James A. Fuxa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10936493Abstract: An example memory system may include a central processing unit (CPU) comprising a CPU cache, a storage class memory, a volatile memory and a memory controller. The memory controller is to store, in the storage class memory, a first cache line including first data and a first directory tag corresponding to the first data. The memory controller is to further store, in the storage class memory, a second cache line including second data and a second directory tag corresponding to the second data. The memory controller is to store, in the volatile memory, a third cache line that comprises the first directory tag and the second directory tag, the third cache line excluding the first data and the second data.Type: GrantFiled: June 19, 2019Date of Patent: March 2, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Robert C. Elliott, James A. Fuxa
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Publication number: 20200401521Abstract: An example memory system may include a central processing unit (CPU) comprising a CPU cache, a storage class memory, a volatile memory and a memory controller. The memory controller is to store, in the storage class memory, a first cache line including first data and a first directory tag corresponding to the first data. The memory controller is to further store, in the storage class memory, a second cache line including second data and a second directory tag corresponding to the second data. The memory controller is to store, in the volatile memory, a third cache line that comprises the first directory tag and the second directory tag, the third cache line excluding the first data and the second data.Type: ApplicationFiled: June 19, 2019Publication date: December 24, 2020Inventors: Robert C. Elliott, James A. Fuxa
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Patent number: 10175742Abstract: A backup power and load discovery system can include a shared backup power supply controlled by a backup power control module, and a node coupled to the shared backup power supply, wherein the node supports a plurality of loads and includes system firmware to determine a subset of the plurality of loads that are to be protected by the shared backup power supply; and the system firmware to communicate the subset between the node and the shared backup power control module.Type: GrantFiled: September 5, 2014Date of Patent: January 8, 2019Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Edgar Hance, James A. Fuxa, Justin H. Park, David K. Altobelli, Marc W. Galloway
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Patent number: 9983927Abstract: Methods and apparatuses for enhanced protection of data stored in a non-volatile memory system involve a controller capable of adapting to the failure of one or more non-volatile memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different non-volatile memory device. The controller also detects failure of a non-volatile memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed non-volatile memory device.Type: GrantFiled: September 7, 2015Date of Patent: May 29, 2018Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, James A. Fuxa
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Publication number: 20170212569Abstract: Example implementations relate to load discovery. For example, a load discovery system can include a shared backup power supply controlled by a backup power control module, and a node coupled to the shared backup power supply, wherein the node supports a plurality of loads, and the shared backup power supply powers the plurality of loads when the node is powered off, and a baseboard management control (BMC) unit coupled to the node, the BMC unit to discover the plurality of loads.Type: ApplicationFiled: October 31, 2014Publication date: July 27, 2017Inventors: David C. Valdez, Han Wang, James A. Fuxa
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Publication number: 20170192489Abstract: A backup power and load discovery system can include a shared backup power supply controlled by a backup power control module, and a node coupled to the shared backup power supply, wherein the node supports a plurality of loads and includes system firmware to determine a subset of the plurality of loads that are to be protected by the shared backup power supply; and the system firmware to communicate the subset between the node and the shared backup power control module.Type: ApplicationFiled: September 5, 2014Publication date: July 6, 2017Inventors: Edgar Hance, James A Fuxa, Justin H. Park, David K. Altobelli, Marc W. Galloway
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Patent number: 9501235Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.Type: GrantFiled: February 1, 2016Date of Patent: November 22, 2016Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
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Publication number: 20160162211Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.Type: ApplicationFiled: February 1, 2016Publication date: June 9, 2016Inventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
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Patent number: 9250991Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.Type: GrantFiled: December 31, 2014Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
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Publication number: 20150378819Abstract: Methods and apparatuses for enhanced protection of data stored in a non-volatile memory system involve a controller capable of adapting to the failure of one or more non-volatile memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different non-volatile memory device. The controller also detects failure of a non-volatile memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed non-volatile memory device.Type: ApplicationFiled: September 7, 2015Publication date: December 31, 2015Inventors: Holloway H. Frost, Charles J. Camp, James A. Fuxa
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Patent number: 9128871Abstract: Methods and apparatuses for enhanced protection of data stored in a non-volatile memory system involve a controller capable of adapting to the failure of one or more non-volatile memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different non-volatile memory device. The controller also detects failure of a non-volatile memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed non-volatile memory device.Type: GrantFiled: January 13, 2014Date of Patent: September 8, 2015Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, James A. Fuxa
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Publication number: 20150113341Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.Type: ApplicationFiled: December 31, 2014Publication date: April 23, 2015Inventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
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Patent number: 8943263Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.Type: GrantFiled: May 28, 2012Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
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Patent number: 8775772Abstract: Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string.Type: GrantFiled: December 21, 2009Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: James A. Fuxa, Lance W. Shelton, Justin C. Haggard
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Publication number: 20140143636Abstract: Methods and apparatuses for enhanced protection of data stored in a non-volatile memory system involve a controller capable of adapting to the failure of one or more non-volatile memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different non-volatile memory device. The controller also detects failure of a non-volatile memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed non-volatile memory device.Type: ApplicationFiled: January 13, 2014Publication date: May 22, 2014Applicant: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, James A. Fuxa
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Patent number: 8631274Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of adapting to the failure of one or more FLASH memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different FLASH memory device. The controller also detects failure of a FLASH memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed FLASH memory device.Type: GrantFiled: May 7, 2012Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, James A. Fuxa
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Patent number: 8631273Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of adapting to the failure of one or more FLASH memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different FLASH memory device. The controller also detects failure of a FLASH memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed FLASH memory device.Type: GrantFiled: May 7, 2012Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Holloway H. Frost, Charles J. Camp, James A. Fuxa
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Patent number: 8443136Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of using variable size page stripes in the memory system. The controller is configured to store data such that each page stripe comprises a plurality of data pages, with each data page in the page stripe being stored in a different FLASH memory chip. The controller is also configured to maintain one or more buffers containing information reflecting blocks of memory within the FLASH memory chips that have been erased and are available for information storage, and to dynamically determine the number of data pages to be included in a page stripe based on the information in the one or more buffers such that a first page stripe and a second page stripe can have different numbers of data pages.Type: GrantFiled: December 17, 2010Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Holloway H. Frost, James A. Fuxa, Charles J. Camp
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Publication number: 20120233391Abstract: Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.Type: ApplicationFiled: May 28, 2012Publication date: September 13, 2012Applicant: TEXAS MEMORY SYSTEMS, INC.Inventors: Holloway H. Frost, Charles J. Camp, Timothy J. Fisher, James A. Fuxa, Lance W. Shelton
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Publication number: 20120221888Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of adapting to the failure of one or more FLASH memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different FLASH memory device. The controller also detects failure of a FLASH memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed FLASH memory device.Type: ApplicationFiled: May 7, 2012Publication date: August 30, 2012Applicant: TEXAS MEMORY SYSTEMS, INC.Inventors: Holloway H. Frost, James A. Fuxa, Charles J. Camp