Abstract: The disclosure is of apparatus for generating raster scans on an oscilloscope combined with an electron microscope used for scanning and examining semiconductor devices. A scanning electron microscope can be operated to generate artificial or induced faults in semiconductor memories, and the raster scanner, in carrying out a scan, will visually display on the oscilloscope natural and artificial or induced faulty locations or cells in semiconductor memories. The semiconductor memory under test is positioned at different locations in the microscope, at each of which an artificial fault is generated until a position is reached, at which the artificial fault coincides, or nearly coincides, with the natural fault location as displayed by the raster scanner. When this is achieved, the electron microscope can then be used to examine the naturally faulty location or cell to determine the reason for the fault.

Abstract: The disclosure is of a system including a counter for generating a sequence of logic signals forming a truth table on its output lines. Some of the lines are coupled directly to a memory or buffer and then to a utilization means. Others are coupled through a controllable multiplexer to the memory so that overall, as the counter counts, a desired logic sequence or truth table appears on all of the lines feeding into the memory.The multiplexer can be operated so that several different sizes of matrices can be scanned by suitably setting the controllable multiplexer, and one use of the invention is for scanning and testing memories of various sizes.

Abstract: The disclosure is of an integrated circuit assembly comprising a base which carries an integrated circuit chip and a cover which protects the chip. The cover has embedded therein a capacitor which has its two leads connected to, or in contact with, two leads on the base when the cover is assembled with the base.

Abstract: The fixture comprises an insulating housing of synthetic resinous material which carries two sets of switches which number, in total, the number of terminals on an integrated circuit (IC) to be tested. Each switch has a manually operable arm or lever which can be placed in three separate positions, an upper position, a center position, and a lower position; and the switch has three terminals, an upper terminal, a center terminal, and a lower terminal, one for each position of the operable arm. All of the upper switch terminals are connected together to a first common plug, and all of the lower switch terminals are connected together to a second common plug, the two plugs being adapted to be inserted into a test device such as a curve tracer. Each center terminal is connected separately to a terminal on a zero-insertion force socket, into which the pins of the integrated circuit under test can be inserted.

Abstract: .[.The disclosure is of.]. .Iadd.An .Iaddend.apparatus for generating raster scans on an oscilloscope combined with an electron microscope used for scanning and examining semiconductor devices. A scanning electron microscope can be operated to generate artificial or induced faults in semiconductor memories, and the raster scanner, in carrying out a scan, will visually display on the oscilloscope natural and artificial or induced faulty locations or cells in semiconductor memories. The semiconductor memory under test is positioned at different locations in the microscope, at each of which an artificial fault is generated until a position is reached, at which the artificial fault coincides, or nearly coincides, with the natural fault location as displayed by the raster scanner. When this is achieved, the electron microscope can then be used to examine the naturally faulty location or cell to determine the reason for the fault.