Patents by Inventor James A. Teplik
James A. Teplik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10249615Abstract: A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.Type: GrantFiled: January 12, 2015Date of Patent: April 2, 2019Assignee: NXP USA, INC.Inventors: Bruce M. Green, James A. Teplik
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Patent number: 9972703Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.Type: GrantFiled: August 1, 2016Date of Patent: May 15, 2018Assignee: NXP USA, INC.Inventors: Jenn Hwa Huang, James A. Teplik
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Patent number: 9893156Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.Type: GrantFiled: March 28, 2017Date of Patent: February 13, 2018Assignee: NXP USA, INC.Inventors: Jenn Hwa Huang, Tianwei Sun, James A. Teplik
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Publication number: 20170200794Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.Type: ApplicationFiled: March 28, 2017Publication date: July 13, 2017Inventors: JENN HWA HUANG, TIANWEI SUN, JAMES A. TEPLIK
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Patent number: 9647075Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.Type: GrantFiled: September 16, 2015Date of Patent: May 9, 2017Assignee: NXP USA, INC.Inventors: Jenn Hwa Huang, Tianwei Sun, James A. Teplik
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Publication number: 20170077245Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.Type: ApplicationFiled: September 16, 2015Publication date: March 16, 2017Inventors: Jenn Hwa Huang, Tianwei Sun, James A. Teplik
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Publication number: 20160343833Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.Type: ApplicationFiled: August 1, 2016Publication date: November 24, 2016Inventors: Jenn Hwa Huang, James A. Teplik
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Patent number: 9425267Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.Type: GrantFiled: March 14, 2013Date of Patent: August 23, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Jenn Hwa Huang, James A. Teplik
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Publication number: 20150123168Abstract: A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.Type: ApplicationFiled: January 12, 2015Publication date: May 7, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Bruce M. Green, James A. Teplik
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Patent number: 9024324Abstract: A low leakage current transistor (2) is provided which includes a GaN-containing substrate (11-14) covered by a passivation surface layer (17) in which a T-gate electrode with sidewall extensions (20) is formed and coated with a multi-level passivation layer (30-32) which includes an intermediate etch stop layer (31) which is used to define a continuous multi-region field plate (33) having multiple distances between the bottom surface of the field plate 33 and the semiconductor substrate in the gate-drain region of the transistor.Type: GrantFiled: September 5, 2012Date of Patent: May 5, 2015Assignee: Freescale Semiconductor, Inc.Inventors: James A. Teplik, Bruce M. Green
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Patent number: 8946779Abstract: A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.Type: GrantFiled: February 26, 2013Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, James A. Teplik
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Publication number: 20140264360Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEXASInventors: Jenn Hwa HUANG, James A. TEPLIK
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Publication number: 20140239346Abstract: A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.Type: ApplicationFiled: February 26, 2013Publication date: August 28, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Bruce M. Green, James A. Teplik
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Publication number: 20140061659Abstract: A low leakage current transistor (2) is provided which includes a GaN-containing substrate (11-14) covered by a passivation surface layer (17) in which a T-gate electrode with sidewall extensions (20) is formed and coated with a multi-level passivation layer (30-32) which includes an intermediate etch stop layer (31) which is used to define a continuous multi-region field plate (33) having multiple distances between the bottom surface of the field plate 33 and the semiconductor substrate in the gate-drain region of the transistor.Type: ApplicationFiled: September 5, 2012Publication date: March 6, 2014Inventors: James A. Teplik, Bruce M. Green
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Patent number: 5312764Abstract: A method of decoupling a step for modulating a defect density from a step for modulating a junction depth. A semiconductor substrate (30) having a portion doped with a dopant (34) is heated to a pre-oxidation anneal temperature in a pre-oxidation anneal step (23). After the pre-oxidation anneal step (23), the semiconductor substrate (30) undergoes an oxidation step (25) which serves as a step for modulating the defect density. Subsequent to the oxidation step (25), the semiconductor substrate (30) undergoes a drive-in step (27) which serves as a step for modulating the junction depth. Then, the temperature of the semiconductor substrate (30) is lowered to allow further processing of the semiconductor substrate (30).Type: GrantFiled: May 28, 1993Date of Patent: May 17, 1994Assignee: Motorola, Inc.Inventors: Clifford I. Drowley, James A. Teplik, Erik W. Egan