Abstract: An approach is provided in which a design tool executes static timing analysis of an integrated circuit design using a first set of timing values corresponding to a first set of layout properties of a transistor included in a standard cell utilized by the integrated circuit design. When the design tool determines that the static timing analysis generates a timing violation within a violation budget, the design tool selects a second set of timing values of the standard cell corresponding to a second set of layout properties of the transistor. The design tool determines that re-execution of the static timing analysis using the second set of timing values resolves the timing violation and, in turn, generates mask layer data that includes the second set of layout properties.

Abstract: An approach is provided in which a design tool executes static timing analysis of an integrated circuit design using a first set of timing values corresponding to a first set of layout properties of a transistor included in a standard cell utilized by the integrated circuit design. When the design tool determines that the static timing analysis generates a timing violation within a violation budget, the design tool selects a second set of timing values of the standard cell corresponding to a second set of layout properties of the transistor. The design tool determines that re-execution of the static timing analysis using the second set of timing values resolves the timing violation and, in turn, generates mask layer data that includes the second set of layout properties.

Abstract: An electrically erasable programmable semiconductor memory cell having an associated conducting column line, read/write line, sense line and row line includes a floating gate transistor which controls the discharge of the read/write line to the column line during read cycles. During write cycles and precharging of said read/write line the column line is made electrically floating so that a faster precharge time and hence access time is obtained and so that access time is independent on the conducting state of the floating gate transistor resulting at commencement of a read cycle.

Abstract: An electrically erasable programmable memory cell of the four transistor type in which a floating gate transistor has one end of its source to drain path coupled to the write line and the other end to the read line through a read switch. Its control gate is connected to the sense line. A tunnel device has a cathode connected to the floating gate of the floating gate transistor, and an anode through a write switch connected to the write line. The gates of both the read and write select transistors are connected to the row line. By coupling one end of the read switch to the read line rather than connecting one end of the source to drain path of the floating gate transistor to the read line for unselected cells in which the read switch is off, only the capacitance of one end of the read switch is added to the parasitic capacitance of the read line whether the floating gate of the floating gate transistor has previously been charged negatively or positively.