Patents by Inventor James Aarestad

James Aarestad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
    Patent number: 10868535
    Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: December 15, 2020
    Assignee: STC.UNM
    Inventors: James Plusquellic, James Aarestad
  • SYSTEMS AND METHODS FOR LEVERAGING PATH DELAY VARIATIONS IN A CIRCUIT AND GENERATING ERROR-TOLERANT BITSTRINGS
    Publication number: 20200235735
    Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
    Type: Application
    Filed: April 8, 2020
    Publication date: July 23, 2020
    Inventors: James Plusquellic, James Aarestad
  • Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
    Patent number: 10666256
    Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: May 26, 2020
    Assignee: STC.UNM
    Inventors: James Plusquellic, James Aarestad
  • SYSTEMS AND METHODS FOR LEVERAGING PATH DELAY VARIATIONS IN A CIRCUIT AND GENERATING ERROR-TOLERANT BITSTRINGS
    Publication number: 20190089355
    Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 21, 2019
    Inventors: James Plusquellic, James Aarestad
  • Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
    Patent number: 10230369
    Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: March 12, 2019
    Assignee: STC.UNM
    Inventors: James Plusquellic, James Aarestad
  • SYSTEMS AND METHODS FOR LEVERAGING PATH DELAY VARIATIONS IN A CIRCUIT AND GENERATING ERROR-TOLERANT BITSTRINGS
    Publication number: 20160204781
    Abstract: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
    Type: Application
    Filed: August 28, 2014
    Publication date: July 14, 2016
    Inventors: James Plusquellic, James Aarestad