Abstract: A computer system including individually resettable bus expander bridges is described. A master bus controller provides an interface between at least one processor and at least one independently resettable bus expander bridge associated with one or more expansion buses. A bus expander bridge can be reset independently from the rest of the system when the master bus controller asserts a reset control signal that is applied to the bus expander bridge without affecting the operation of any other bus expander bridges or devices in the computer system not directly coupled to the expansion bus(es) being reset. When a reset control signal is asserted, the bus expander bridge being reset and the bus(es) associated with the bus expander bridge are reset to a default state. Once the reset process has had sufficient time for completion, the reset control signal is deasserted by the master bus controller and the bus expander bridge resumes operation.