Abstract: A refresh circuit selects a candidate bank for refreshing from various banks of a dynamic random access memory (DRAM). Initially, the refresh circuit checks if any bank is idle (e.g., is not targeted for memory operations). If two or more banks are idle, the candidate bank is selected based on a count of accesses targeted to each occupied bank and bank-pair distances between each pair of idle and occupied banks. Conversely, if all banks are occupied, the refresh circuit selects the candidate bank based on a count of data accesses targeted to each bank and/or a count of parity accesses targeted to each bank. Each data access has the same type as that scheduled for execution on the DRAM. Once the candidate bank is selected, the refresh circuit triggers the refresh of the candidate bank.

Abstract: An aspect of the invention is directed towards a data processing system and method including a transaction scheduler configured to process transactions, a tag control circuit coupled to the transaction scheduler configured to detect a fault by comparing output signals, and a controller coupled to the tag control circuit. The controller is configured to receive a transaction request identifying a transaction, generate a unique tag value for the transaction request, load the unique tag value into the transaction scheduler, determine a current unique tag value associated with the transaction being executed, and generate a fault. The system is further configured to generate fault when: (i) the current unique tag value is not found, or (ii) the transactions timeout after a predetermined number of cycles.

Abstract: Aspects of the disclosure are directed to allocating bandwidth. As may be implemented in accordance with one or more embodiments, respective amounts of bandwidth are allocated to respective application groups for each memory access cycle in a set of memory access cycles. Initial bonus bandwidth is provided to a first one of the application groups during one of the memory access cycles. The bonus bandwidth may include at least a portion of bandwidth allocated to and unused by one of the other respective application groups during the memory access cycle. Additional bonus bandwidth is selectively provided to the first application group during one of the memory access cycles based on the initial bonus bandwidth and a maximum amount of bonus bandwidth defined for the set of memory access cycles, in response to bandwidth allocated to one of the other respective application groups during the subsequent memory access cycle being unused.

Abstract: A resonance avoidance system including a resonance avoidance controller configured to insert a delay between sequential transactions on a communication interface separated by an inactive period to avoid stimulating a power distribution network resonance. The resonance avoidance controller may be configured to insert the delay by delaying a second transaction from being driven onto the communication interface after a first transaction in which the delay is sufficient to avoid stimulating the power distribution network resonance. The delay may be inserted by delaying a driver from driving the second transaction by the sufficient delay. The conflict may be detected between first and second commands in a command queue, in which the delay may be inserted by inserting no operation commands between the commands in the command queue. Operational timing values may be stored that are used to detect resonant frequency conflicts.

Abstract: A memory controller includes a transaction scheduler circuit and a command queue. For each access request received by the memory controller, the transaction scheduler circuit is configured to allocate a new entry in a scheduler queue, store an access address corresponding to the access request as a data address into the new entry, generate an error correction code (ECC) address from the data address and store the ECC address into the new entry, and set a corresponding ECC mode field in the new entry to indicate whether the data address or ECC address of the new entry is to be exposed during arbitration. The transaction scheduler circuit, during an arbitration cycle, is configured to select a transaction from the scheduler queue using an exposed address of each valid entry, and is configured to provide the selected transaction to the command queue.

Abstract: Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and command logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a memory scrubber configured to cycle through memory locations and to read data from those locations; a region selector configured to determine when a memory location read by the memory scrubber is within an integrity checked memory region; a runtime integrity check (RTIC) engine connected to a read data path of the memory interface, wherein the RTIC engine is configured to calculate an integrity check value for the RTIC region using data read from the checked memory region by the memory scrubber; and a RTIC controller configured to compare the calculated integrity check value for the checked memory region to a reference integrity check value for the checked memory region.

Abstract: Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and command logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a memory scrubber configured to cycle through memory locations and to read data from those locations; a region selector configured to determine when a memory location read by the memory scrubber is within an integrity checked memory region; a runtime integrity check (RTIC) engine connected to a read data path of the memory interface, wherein the RTIC engine is configured to calculate an integrity check value for the RTIC region using data read from the checked memory region by the memory scrubber; and a RTIC controller configured to compare the calculated integrity check value for the checked memory region to a reference integrity check value for the checked memory region.

Abstract: Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and control logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a read inline encryption engine (IEE) connected to the memory interface, wherein the read IEE is configured to decrypt encrypted data read from the memory; a key selector configured to determine a read memory region associated with the memory read request based upon a read address where the data to be read is stored, wherein the read address is received from the address and control logic; and a key logic configured to select a first key associated with the determined read memory region and provide the selected key to the read IEE.

Abstract: Various embodiments relate to a memory controller, including: a memory interface connected to a memory; an address and control logic connected to the memory interface and a command interface, wherein the address and control logic is configured to receive a memory read request; a read inline encryption engine (IEE) connected to the memory interface, wherein the read IEE is configured to decrypt encrypted data read from the memory; a key selector configured to determine a read memory region associated with the memory read request based upon a read address where the data to be read is stored, wherein the read address is received from the address and control logic; and a key logic configured to select a first key associated with the determined read memory region and provide the selected key to the read IEE.

Abstract: A phase to digital converter (PDC) generates a digital output that represents a phase difference between first and second clocks. The PDC includes a gated ring oscillator (GRO), which includes N signal delay elements coupled together in a ring via a logic gate, wherein a 1st signal delay element of the ring comprises an input coupled to an output of the logic gate, and wherein a Nth signal delay element of the ring comprises an output coupled to a first input of the logic gate. A convertor is coupled to the GRO and configured to generate low order bits of the digital output based on outputs of the logic gate and the N signal delay elements. A first counter includes an input coupled to an output of one of the N signal delay elements or the logic gate, wherein the first counter is configured to generate a first digital counter value.