Abstract: A 3D ultraviolet (UV) imaging LADAR system includes a UV source configured to generate a UV interrogation beam, a sensor configured to receive a UV return beam reflected from a target and to produce an electrical signal, and an imaging module coupled to the sensor and configured to receive the electrical signal and to generate a corresponding 3D image of the target. In one example, the sensor includes a down-shifting device configured to down-shift the UV return beam to a down-shifted light beam of a different wavelength, for example, in the visible or SWIR wavelength ranges.

Abstract: A 3D ultraviolet (UV) imaging LADAR system includes a UV source configured to generate a UV interrogation beam, a sensor configured to receive a UV return beam reflected from a target and to produce an electrical signal, and an imaging module coupled to the sensor and configured to receive the electrical signal and to generate a corresponding 3D image of the target. In one example, the sensor includes a down-shifting device configured to down-shift the UV return beam to a down-shifted light beam of a different wavelength, for example, in the visible or SWIR wavelength ranges.

Abstract: An integrated application specific integrated circuit having a detection layer, a time delayed integration capability, data acquisition electronics, and a readout function is provided for detecting breast cancer in women. The detection layer receives x-ray radiation and converts the received energy to electron pairs, one of which is received by pixels. The time delay integration is on the chip and a part of the readout architecture. The detector may be a hybrid silicon detector (SiPD), a CdZnTe detector, or a GaAs detector.

Abstract: Disclosed is a LADAR system and a method for operating same. The LADAR system includes circuitry for generating the electrical signal with an optical signal detector using N discrete samples; a bank of M parallel sample/hold circuit unit cells individual ones of which operate with an associated sample/hold clock, where each sample/hold clock is shifted in time by a fixed or programmable amount ?t relative to a sample/hold clock of an adjacent sample/hold circuit unit cell; and further includes circuitry for sequentially coupling a sampled value of the electrical signal from a first output of individual ones of at least some of the M parallel sample/hold circuit unit cells to an analog to digital converter circuit. Each of the M parallel sample/hold circuit unit cells has a second output for outputting a digital signal for indicating the state (low or high) during a time that the associated sample/hold clock allowing for time of arrival determination.