Patents by Inventor James B. Burr

James B. Burr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8593169
    Abstract: Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indicator of the integrated circuit at the desired specific operating frequency. The predetermined value is stored in a data structure within a computer usable media. The data structure comprises a plurality of frequency specific predetermined values for a variety of operating frequencies. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the measured behavior of the integrated circuit.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: November 26, 2013
    Inventors: Kleanthes G. Koniaris, James B. Burr
  • Patent number: 8461891
    Abstract: A method and system of voltage compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of voltage compensation.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: June 11, 2013
    Inventors: Robert Fu, Neal A. Osborn, James B. Burr
  • Patent number: 8420472
    Abstract: Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: April 16, 2013
    Inventors: Kleanthes G. Koniaris, Robert Paul Masleid, James B. Burr
  • Patent number: 8415730
    Abstract: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: April 9, 2013
    Inventors: James B Burr, Robert Fu
  • Patent number: 8370785
    Abstract: Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: February 5, 2013
    Inventors: David R. Ditzel, James B. Burr
  • Publication number: 20120319721
    Abstract: Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior.
    Type: Application
    Filed: August 16, 2012
    Publication date: December 20, 2012
    Inventors: Kleanthes G. Koniaris, James B. Burr
  • Patent number: 8319515
    Abstract: Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: November 27, 2012
    Inventors: Robert Paul Masleid, James B. Burr
  • Publication number: 20120281483
    Abstract: Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog.
    Type: Application
    Filed: July 16, 2012
    Publication date: November 8, 2012
    Inventors: Robert Paul Masleid, James B. Burr
  • Patent number: 8298896
    Abstract: Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: October 30, 2012
    Inventors: James B. Burr, Archisman Bagchi, Jawad Nasrullah
  • Patent number: 8253434
    Abstract: Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: August 28, 2012
    Inventors: Kleanthes G. Koniaris, James B. Burr
  • Patent number: 8222914
    Abstract: Systems and methods for adjusting threshold voltage. A threshold voltage of a transistor of an integrated circuit is measured. A bias voltage, which when applied to a body well of the transistor corrects a difference between the threshold voltage and a desired threshold voltage for the transistor, is determined. The bias voltage is encoded into non-volatile storage on the integrated circuit. The non-volatile storage can be digital and/or analog.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: July 17, 2012
    Inventors: Robert Paul Masleid, James B. Burr
  • Patent number: 8146037
    Abstract: A method for the design and layout for a patterned deep N-well. A tile is specified as a fundamental building block for the deep N-well pattern. The tile comprises a first element on a first layer and may comprise a second element on a second layer. A two dimensional region is covered with an array of contiguous tiles, with the elements on each layer connecting with elements of adjacent tiles to form extended shapes. The array may be converted to a collection of sub-arrays through the removal of tiles. The array or collection of sub-arrays may be merged to produce a first layer pattern and second layer pattern. Design rule checks may be applied to verify the pattern. The first layer shapes and second layer shapes may be edited. The first layer shapes and the second layer shapes may then be combined to produce a deep N-well pattern.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: March 27, 2012
    Inventors: Michael Pelham, James B. Burr
  • Publication number: 20120001651
    Abstract: Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indicator of the integrated circuit at the desired specific operating frequency. The predetermined value is stored in a data structure within a computer usable media. The data structure comprises a plurality of frequency specific predetermined values for a variety of operating frequencies. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the measured behavior of the integrated circuit.
    Type: Application
    Filed: September 16, 2011
    Publication date: January 5, 2012
    Inventors: Kleanthes G. Koniaris, James B. Burr
  • Publication number: 20110300681
    Abstract: Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
    Type: Application
    Filed: August 22, 2011
    Publication date: December 8, 2011
    Inventors: James B. Burr, Archisman Bagchi, Jawad Nasrullah
  • Publication number: 20110296208
    Abstract: Methods and systems for operating a semiconductor device (e.g., a microprocessor) are described. The microprocessor is initially operated at a voltage and frequency that would be within operating limits at any device temperature. Using models that relate device temperature, operating limits and power consumption with voltage and frequency, the amount of supply voltage and a new operating frequency can be selected. The models are periodically consulted thereafter to continue adjusting the supply voltage and operating frequency, so that the microprocessor is caused to operate at very close to its capacity, in particular in those instances when, for example, processor-intensive instructions are being executed.
    Type: Application
    Filed: February 28, 2011
    Publication date: December 1, 2011
    Inventors: Kleanthes G. Koniaris, James B. Burr, Mark Hennecke
  • Publication number: 20110258590
    Abstract: Software controlled transistor body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasing values, wherein the characteristic is enhanced.
    Type: Application
    Filed: June 24, 2011
    Publication date: October 20, 2011
    Inventors: David R. Ditzel, James B. Burr
  • Patent number: 8040149
    Abstract: Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indicator of the integrated circuit at the desired specific operating frequency. The predetermined value is stored in a data structure within a computer usable media. The data structure comprises a plurality of frequency specific predetermined values for a variety of operating frequencies. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the measured behavior of the integrated circuit.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: October 18, 2011
    Inventors: Kleanthes G. Koniaris, James B. Burr
  • Publication number: 20110221029
    Abstract: Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a desirable dynamic condition for circuitry of an integrated circuit. A first dynamic indicator corresponding to the desirable dynamic condition is accessed. Second and third dynamic indicators of the integrated circuit are accessed. A first body biasing voltage is adjusted by an increment so as to change the first dynamic indicator in the direction of the desirable dynamic condition. A second body biasing voltage is adjusted based on a relationship between the second dynamic indicator and the third dynamic indicator.
    Type: Application
    Filed: May 23, 2011
    Publication date: September 15, 2011
    Inventors: Vjekoslav Svilan, James B. Burr
  • Publication number: 20110219245
    Abstract: A method and system of adaptive power control. Characteristics of a specific integrated circuit are used to adaptively control power of the integrated circuit.
    Type: Application
    Filed: May 9, 2011
    Publication date: September 8, 2011
    Inventors: James B. Burr, Andrew Read, Tom Stewart
  • Patent number: 8003471
    Abstract: Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with one embodiment may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: August 23, 2011
    Inventors: James B. Burr, Archisman Bagchi, Jawad Nasrullah